Stepped Semiconductor Package Frame for Compact Wire Bond Routing
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Solution Overview
Problem
The existing semiconductor devices increase in size due to the need for a predetermined width of the frame to secure the joint strength between the base substrate and the frame when mounting a semiconductor chip and a capacitive component, which hinders downsizing.
Innovation Solution
A semiconductor device design featuring a frame with a step configuration, where a capacitive component is mounted on a conductor pattern of the frame's inner surface, and a cover seals the semiconductor chip, allowing for reduced bonding wire lengths and interference, thereby downsizing the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the frame width is increased to secure joint strength between base substrate and frame, then the joint strength is improved, but the device size increases
Solution Approach 1:
The frame is designed with a step configuration that utilizes vertical dimension (height) to create mounting surfaces at different levels. The first upper surface is positioned at a first height while the second upper surface is at a second height higher than the first height, allowing components to be mounted at different vertical levels without requiring increased horizontal frame width, thus maintaining joint strength while reducing device size.
Solution Approach 2:
The frame's upper surface is segmented into two distinct levels: a first upper surface at a lower height and a second upper surface at a higher height. This segmentation allows the capacitive component to be mounted on the elevated second upper surface while the semiconductor chip remains on the base substrate, optimizing space utilization and reducing the overall device footprint without compromising structural integrity.
2Area of stationary object
If the device is downsized by reducing frame width, then device size is reduced, but bonding wires may interfere with each other
Solution Approach 1:
By utilizing the vertical dimension to create a stepped frame structure with different height levels, the invention allows bonding wires to be routed at different vertical planes. The first bonding wire connects components on the lower first upper surface while the second bonding wire connects components on the higher second upper surface, spatially separating the bonding wires and preventing interference even in a compact device size.
Solution Approach 2:
The frame provides locally differentiated mounting surfaces at different heights. The second upper surface is elevated to create a distinct spatial zone for mounting the capacitive component and routing its bonding wires, while the first upper surface serves for other components. This local spatial differentiation prevents bonding wire interference without requiring overall device size increase.
Data Source
AI summary
A semiconductor device includes: a conductive base substrate; a semiconductor chip mounted on the base substrate and having a signal pad; a frame configured to surround the semiconductor chip, to be mounted on the base substrate, and to include a step having an inner first upper surface and an outer second upper surface higher than the first upper surface in a plan view, wherein a first conductor pattern provided on the first upper surface is electrically connected to the base substrate; a capacitive component mounted on the first conductor pattern; a signal terminal mounted on the second upper surface of the frame; a first bonding wire configured to electrically connect the signal pad and an upper surface of the capacitive component; and a second bonding wire configured to electrically connect the upper surface of the capacitive component and the signal terminal.