Stepped Pad Structure for 3D Memory RC Delay Reduction
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Solution Overview
Problem
As two-dimensional non-volatile memory devices approach their physical scaling limits, there is a need for improved manufacturing methods and structures to enhance the reliability and efficiency of three-dimensional non-volatile memory devices, particularly in reducing the distance between circuit and cell structures to increase program speed and integration density.
Innovation Solution
A semiconductor device and manufacturing method involving a pad structure with stepped pads and openings that electrically couple pads and cell structures, reducing the distance between the circuit and cell structures, and using a stacked structure with alternating conductive and insulating layers to form memory cells vertically, thereby improving integration density and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional non-volatile memory device structure is used, then manufacturing process is simpler, but integration density and program speed are limited due to physical scaling limits
Solution Approach 1:
The patent transitions from a two-dimensional memory structure to a three-dimensional structure by stacking memory cells vertically. The memory device includes a substrate with multiple layers including first and second cell regions with vertically stacked gate electrodes, channel layers, and insulating layers, enabling increased integration density by utilizing the vertical dimension for memory cell arrangement.
Solution Approach 2:
The patent implements a nested structure where multiple functional layers are stacked within each other vertically. The memory device contains nested layers including gate electrodes, channel layers, blocking insulating layers, and interlayer insulating layers arranged in a vertical stack, with each layer nested within the structure formed by previous layers.
2Speed
If distance between circuit and cell structures is increased, then manufacturing is easier, but RC delay increases and program speed decreases
Solution Approach 1:
The patent segments the memory device into distinct functional regions including first and second cell regions with separate gate electrode stacks, allowing independent optimization of each region. The circuit structures are also segmented and positioned in specific locations beneath the pad structure, enabling reduced distance to cell structures while maintaining manufacturing feasibility through modular segmentation.
Solution Approach 2:
The patent reduces the distance between circuit and cell structures by utilizing vertical stacking to bring circuit elements closer to memory cells in the z-direction. The pad structure with openings exposes circuit elements vertically, reducing the horizontal distance and enabling shorter interconnect paths for faster signal transmission.
3Manufacturing precision
If pad area is increased, then electrical coupling is easier, but integration density decreases
Solution Approach 1:
The patent utilizes vertical stacking to achieve electrical coupling in the vertical dimension rather than requiring large horizontal pad areas. The pad structure includes openings that extend vertically to expose circuit elements, allowing electrical coupling through the pad structure via vertically extending interconnects, thereby reducing the horizontal footprint of pads while maintaining effective electrical connection.
Solution Approach 2:
The patent introduces a pad structure with openings as an intermediary element that facilitates electrical coupling between external contacts and underlying circuit elements. The openings in the pad structure serve as conduits for interconnects to reach circuit elements, enabling electrical coupling without requiring large direct contact areas between pads and circuits.
Data Source
AI summary
A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. The pad structure may have a plurality of stepped structures. The circuit may be disposed under the pad structure. The one or more openings may pass through the pad structure, and may expose the circuit. The one or more openings may be disposed between the plurality of stepped structures.