Stepped Pad Structure for 3D Memory Integration Density
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Solution Overview
Problem
As two-dimensional non-volatile memory technology reaches its physical scaling limit, there is a need for improved manufacturing methods to enhance the reliability and efficiency of three-dimensional non-volatile memory devices by optimizing the structure and interconnection of cell structures and pad structures in semiconductor devices.
Innovation Solution
The semiconductor device incorporates a pad structure with stepped configurations and dummy stepped structures that are electrically connected to cell structures, allowing for reduced distance between the circuit and cell structures, and utilizing these structures to function as wiring lines, thereby simplifying processes and reducing the area of the pad region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional non-volatile memory technology is used, then manufacturing process is simple, but physical scaling limit is reached and integration density cannot be improved
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked structure, where memory cells are arranged vertically across multiple layers. This dimensional change enables continued scaling and improved integration density by utilizing the vertical space above the substrate rather than being constrained to a planar layout.
Solution Approach 2:
The patent implements a stacked memory structure where multiple memory cell layers are nested vertically, with each layer containing complete sets of word lines, bit lines, and memory cells. This nesting approach allows multiple functional layers to be integrated within a compact vertical space, significantly increasing storage capacity per unit area.
2Manufacturing precision
If pad structure area is reduced, then integration density is improved, but wiring connection complexity increases
Solution Approach 1:
The patent combines multiple functions into the pad structure: it serves as both the electrical connection interface and the wiring line extension. The pad structure includes stacked pads at different levels that directly connect to corresponding memory cell layers, eliminating the need for separate wiring layers and reducing overall pad region area while maintaining connectivity.
Solution Approach 2:
The patent utilizes vertical stacking of pads in the pad structure, with pads arranged at different height levels corresponding to different memory cell layers. This three-dimensional pad arrangement reduces the horizontal footprint of the pad region while providing sufficient connection points for all memory cell layers through vertical vias and conductive structures.
3Speed
If distance between circuit and cell structures is reduced, then RC delay is reduced and program speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the pad structure and its conductive components before completing the memory cell structure fabrication. This preliminary formation of connection structures allows subsequent alignment processes to reference already-formed pads and vias, reducing the cumulative alignment error that would occur if all structures were formed simultaneously from scratch.
Solution Approach 2:
The patent divides the interconnection structure into discrete segments: pads at the substrate level, vertical vias connecting to upper layers, and horizontal conductors within each memory cell layer. This segmentation allows each component to be optimized and manufactured independently with appropriate precision requirements, rather than requiring ultra-precise monolithic alignment of all components.
Data Source
AI summary
A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other.