Stepped Passivation Layer for Semiconductor Package Delamination

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Solution Overview

Problem

The existing technologies face challenges in reducing delamination between polymer planarization layers and passivation layers in semiconductor package formation, which affects the reliability and durability of the package components.

Innovation Solution

A stepped passivation layer is formed with specific etching processes to create steps that enhance stress distribution and reduce delamination, allowing for better adhesion between the passivation and polymer layers, and enabling the formation of conductive features like Under-Bump Metallurgy (UBM) to connect with redistribution lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a planar passivation layer is used, then the manufacturing process is simpler, but delamination occurs between the polymer planarization layer and passivation layer

Engineering Contradiction:
Improveresistance to delaminationVSAvoidpassivation layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The passivation layer is segmented into multiple stepped levels instead of a single planar layer. The etching process creates first steps and second steps at different heights, dividing the originally uniform passivation layer into distinct segments that provide multiple bonding interfaces with the polymer planarization layer, thereby reducing delamination risk.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The passivation layer structure transitions from a two-dimensional planar configuration to a three-dimensional stepped configuration. By introducing vertical height variations through selective etching, the structure gains an additional dimensional aspect that increases the bonding surface area and creates mechanical interlocking features with the overlying polymer layer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a stepped passivation layer is formed, then delamination resistance increases, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvestructural integrityVSAvoidetching process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The stepped structure is prepared in advance through selective etching of the passivation layer before the polymer planarization layer is deposited. This preliminary creation of steps ensures that when the polymer layer is later applied, it naturally conforms to the stepped topology, creating inherent mechanical interlocking without requiring additional post-processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etching process parameters are modified to selectively remove portions of the passivation layer at specific locations, creating steps with controlled depths and dimensions. By adjusting etching time, power, and chemistry, the step heights and widths are precisely controlled to optimize both delamination resistance and compatibility with subsequent processing steps.

Inventive Principle:
Principle #35Parameter changes

3Strength

If the passivation layer is etched to form steps, then stress distribution improves, but the manufacturing time increases

Engineering Contradiction:
Improvestress distributionVSAvoidproduction time
Core Design Contradiction:
StrengthVSLoss of time

Solution Approach 1:

The passivation layer is divided into multiple stepped segments that create distributed stress relief zones. Each step acts as an independent stress management feature, breaking up concentrated stress paths that would exist in a planar structure. This segmentation approach improves stress distribution while using a single etching operation rather than multiple sequential steps.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240222194A1Package component with stepped passivation layer
Publication Date: 2024.07.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240222194A1 patent drawing
  • US20240222194A1 patent drawing
  • US20240222194A1 patent drawing

AI summary

A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.