Stepped Passivation Layer Structure for Package Delamination Resistance
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Solution Overview
Problem
The existing semiconductor package formation processes face challenges with delamination issues between the passivation layer and the polymer planarization layer, which can lead to reliability concerns for the electrical connections and overall package integrity.
Innovation Solution
A stepped passivation layer is formed with specific etching processes to create steps that reduce delamination risks, allowing for better stress distribution and increased resistance to interface delamination between the passivation layers, polymer planarization layer, and redistribution lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional planar passivation layer is formed, then the manufacturing process is simple, but delamination occurs between the passivation layer and polymer planarization layer
Solution Approach 1:
The passivation layer is segmented into multiple stepped levels instead of a single planar layer. The etching process creates first and second steps at different heights, which segments the interface between the passivation layer and polymer planarization layer. This segmentation distributes stress across multiple interfaces, preventing delamination that would occur in a conventional single-level planar structure.
2Reliability
If the passivation layer is made planar, then the manufacturing process is straightforward, but stress concentration leads to delamination
Solution Approach 1:
Different regions of the passivation layer are created with different heights (first step and second step), providing local quality variation. The first step region and second step region have different elevations, which allows stress to be distributed locally across multiple levels rather than concentrated at a single planar interface. This local quality differentiation enhances package integrity while managing manufacturing complexity.
Data Source
AI summary
A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.