Stepped Peripheral Structures for NAND Flash Memory Integration
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Solution Overview
Problem
Current NAND type flash memory technologies face challenges in achieving high integration without lithography resolution limits, particularly in forming accurate stepped structures for nonvolatile semiconductor memory devices, which can lead to short-circuiting and hinder miniaturization.
Innovation Solution
The implementation of a nonvolatile semiconductor memory device with a peripheral region featuring a stepped structure and an island structure that allows for precise control of the step boundary formation through advanced lithography and etching techniques, using resist position measurement and compensation to ensure accurate placement and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If advanced lithography and etching techniques are used to form accurate stepped structures, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The peripheral region is divided into multiple stepped structures with different heights, creating distinct levels that can be independently controlled. This segmentation allows precise formation of step boundaries by treating each level as a separate manufacturing target, thereby improving manufacturing precision while managing complexity through modular design
Solution Approach 2:
The invention transitions from two-dimensional planar structures to three-dimensional stepped structures by adding vertical dimensionality. Multiple conductive layers are stacked at different heights, creating a multi-level peripheral region that enables accurate step boundary formation through vertical separation rather than relying solely on lateral lithographic resolution
2Productivity
If stacked type NAND flash memory is used to achieve high integration, then productivity is improved, but manufacturing precision deteriorates due to lithography resolution limits
Solution Approach 1:
The invention exploits the vertical dimension by stacking multiple conductive layers at different heights in the peripheral region. This three-dimensional approach allows high integration of memory cells while forming stepped structures that are defined by vertical layer stacking rather than lateral lithographic patterning, thereby overcoming lithography resolution limits
Solution Approach 2:
Multiple conductive layers are nested vertically within the peripheral region, with each layer positioned at a different height level. This nested arrangement enables high integration density by packing multiple functional layers in the vertical direction, achieving productivity improvement without compromising manufacturing precision since each nested layer can be formed using standard lithography processes
Data Source
AI summary
A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.