Stepped Conductive Pillars for Fine-Pitch ELK Stress Relief
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Solution Overview
Problem
Extremely low-k (ELK) dielectric materials in semiconductor chips face structural weaknesses due to reduced hardness and mechanical modulus, leading to issues like delamination and cracking under chip-package interactions, and fine pitch interconnects increase stress on these materials, while solutions to mitigate stress either cause solder bridging or require reducing the size of the under-bump metallization layer.
Innovation Solution
The implementation of semiconductor chips with stepped conductive pillars, where the base portion of the pillar has a greater width than the end portion, allowing for a wider under-bump metallization layer to reduce stress on the ELK material and maintain a fine pitch without increasing the risk of solder bridging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the size of the under-bump metallization layer is increased to reduce stress on ELK material, then stress on ELK material is reduced, but the pitch between interconnects increases causing solder bridging
Solution Approach 1:
The conductive pillar is divided into two distinct portions: a first portion with a larger cross-sectional area that provides stress distribution, and a second portion with a smaller cross-sectional area that maintains fine pitch. This segmentation allows each portion to fulfill different functional requirements simultaneously.
Solution Approach 2:
Different portions of the conductive pillar have different cross-sectional areas tailored to local requirements: the base portion has a larger area to reduce stress on ELK material, while the top portion has a smaller area to maintain fine pitch between interconnects. This local differentiation resolves the contradiction between stress resistance and pitch maintenance.
2Reliability
If ELK dielectric materials are used to reduce parasitic capacitance and improve switching speeds, then electrical performance is improved, but structural integrity deteriorates due to reduced hardness and mechanical modulus
Solution Approach 1:
The conductive pillar acts as an intermediary structure between the ELK dielectric material and the solder bump. By providing a stepped geometry with a larger base portion, it distributes mechanical stresses away from the ELK material, protecting it from damage while allowing the ELK material to maintain its electrical performance benefits.
3Productivity
If fine pitch interconnects are implemented to increase density, then chip functionality is improved, but stress on ELK material increases causing delamination and cracking
Solution Approach 1:
The conductive pillar is segmented into portions with different cross-sectional areas, allowing the structure to accommodate fine pitch requirements while the enlarged base portion distributes stress to prevent ELK material failure.
Solution Approach 2:
The conductive pillar exhibits local quality variation with a larger base portion for stress distribution and a smaller top portion for maintaining fine pitch, enabling high interconnect density without compromising ELK material integrity.
Data Source
AI summary
In an implementation, a semiconductor chip includes a device layer, an interconnect layer fabricated on the device layer, the interconnect layer including a conductive pad, and a conductive pillar coupled to the conductive pad. The conductive pillar includes at least a first portion having a first width and a second portion having a second width, the first portion being disposed between the second portion and the conductive pad, wherein the first width of the first portion is greater than the second width of the second portion.