Stepped Protective Layer in Semiconductor Packages for Dense Terminals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packages face limitations in reducing size, maintaining circuit integration density, and ensuring physical and electrical reliability due to the increasing number of terminals and mounting pads, which leads to deteriorated performance and increased package size.
Innovation Solution
A semiconductor package design featuring an insulating layer with a protective layer having a stepped structure, where the protective layer includes a first region overlapping the semiconductor device and a second region surrounding it, with a conductive bonding part covered by the second region to minimize stress and improve manufacturing processability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of mounting pads and openings in the first insulating layer is increased to accommodate more terminals, then the number of terminals supported increases, but the package size increases and circuit integration density deteriorates
Solution Approach 1:
The patent transitions from a single-layer insulating structure to a multi-layer insulating structure with different heights. The first insulating layer contains openings for mounting pads, while the second insulating layer is formed at a different height level, allowing three-dimensional arrangement of electrical connections. This vertical dimensionality change enables more terminals to be accommodated without increasing the planar package footprint, thus resolving the contradiction between terminal quantity and package size.
Solution Approach 2:
The insulating structure is segmented into multiple layers (first insulating layer and second insulating layer) with different functions and heights. The first insulating layer handles mounting pad connections, while the second insulating layer provides additional insulation and structural support at a different elevation. This segmentation allows independent optimization of each layer, enabling increased terminal density without compromising package compactness.
2Area of stationary object
If the minimum size of openings in the first insulating layer is reduced to fit more mounting pads, then circuit integration density improves, but manufacturing precision requirements increase and reliability deteriorates
Solution Approach 1:
Instead of reducing opening sizes in a single layer, the patent adds a second insulating layer at a different height. This allows mounting pads to be distributed across multiple vertical levels, effectively increasing the available area for pad placement without requiring smaller openings in any single layer. The multi-layer approach maintains manufacturable opening sizes while achieving higher integration density.
3Quantity of substance
If the package size is increased to accommodate all mounting pads, then all terminals can be connected, but the overall package becomes larger and less compact
Solution Approach 1:
The patent utilizes the vertical dimension by forming a second insulating layer at a different height than the first insulating layer. This three-dimensional configuration allows mounting pads and electrical connections to be arranged in multiple vertical levels, effectively packing more terminals into a compact horizontal footprint. The vertical stacking enables increased terminal capacity without proportionally increasing package length or width.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor package according to an embodiment includes an insulating layer; an electrode part disposed on the insulating layer; and a protective layer disposed on the electrode part, wherein the protective layer includes a first region provided around an upper surface of the protective layer; and a second region excluding the first region, and a step is provided between an upper surface of the first region and an upper surface of the second region.