Stepped Seal Ring Structure for SoIC Corner Bonding

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Solution Overview

Problem

The integration of multiple device dies in a System on Integrate Chip (SoIC) package leads to cracking and non-bonding issues at the corners due to thermal stress caused by differing coefficients of thermal expansion (CTE) between metal seal rings and other package components.

Innovation Solution

The implementation of stepped seal rings with varying aluminum content in the upper and lower portions, where the outer seal ring lacks an upper aluminum portion or has a narrower aluminum upper portion, reducing thermal stress and enhancing bonding integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If uniform aluminum seal rings are used in SoIC packages, then manufacturing simplicity is maintained, but thermal stress causes cracking and non-bonding at corners

Engineering Contradiction:

Improvebonding integrityVSAvoidseal ring structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The seal ring is divided into multiple segments with different aluminum contents: a first seal ring portion with higher aluminum content and a second seal ring portion with lower aluminum content. This segmentation allows each portion to have optimized thermal expansion properties, reducing thermal stress at corners while maintaining bonding integrity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the seal ring are assigned different material compositions tailored to their specific functional requirements. The first seal ring portion has higher aluminum content for regions requiring higher thermal expansion, while the second portion has lower aluminum content for regions requiring lower thermal expansion, optimizing local stress distribution.

Inventive Principle:

Principle #3Local quality

2Adaptability or versatility

If multiple device dies are integrated in SoIC packages, then device functionality is enhanced, but thermal stress-induced cracking occurs at corners

Engineering Contradiction:

Improvedevice functionalityVSAvoidcorner bonding

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The aluminum content parameter is varied across different portions of the seal ring to change the thermal expansion characteristics. By adjusting the aluminum concentration in the first versus second seal ring portions, the thermal stress parameters are optimized to prevent cracking while supporting multi-die integration.

Inventive Principle:

Principle #35Parameter changes

3Stability of the object's composition

If aluminum content is increased in seal rings, then thermal expansion matching is improved, but stress concentration occurs at corners

Engineering Contradiction:

Improvethermal expansion matchingVSAvoidcorner stress

Core Design Contradiction:

Stability of the object's compositionVSStress or pressure

Solution Approach 1:

The seal ring structure implements local quality by assigning different aluminum contents to different portions: the first seal ring portion has higher aluminum content for improved thermal expansion matching in certain regions, while the second seal ring portion has lower aluminum content to reduce stress concentration in other regions.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design minimizes cracking and non-bonding issues at the corners of device dies, ensuring robust and reliable bonding in complex integrated circuit packages.

Implementation Method 1

thermal stress caused by differing coefficients of thermal expansion (CTE) between metal seal rings and other package components

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS12476140B2Semiconductor package including step seal ring and methods forming same

Publication Date: 2025.11.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming a plurality of dielectric layers over a semiconductor substrate, forming a plurality of metal lines and vias in the plurality of dielectric layers, forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers, depositing a first dielectric layer over the plurality of metal lines and vias, and etching the first dielectric layer to form an opening penetrating through the first dielectric layer. After the first dielectric layer is etched, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer. An upper portion of the inner seal ring is then formed to extend into the opening and to join the lower portion of the inner seal ring. A second dielectric layer is deposited to cover the upper portion of the inner seal ring.