Stepped Semiconductor Package Design for Compact Stacking
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Solution Overview
Problem
Existing semiconductor packages face challenges in minimizing size due to wire bonding properties, which make it difficult to achieve a fine pitch and require significant space between chips to prevent electrical shorts, leading to increased thickness.
Innovation Solution
A semiconductor package design featuring stacked semiconductor chips in a stepped configuration with via wirings and redistributions over an encapsulation member, allowing for electrical connection without covering bonding pads, thereby reducing the overall size by eliminating the need for wire bonding margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wire bonding is used to electrically connect semiconductor chips, then electrical connection is achieved, but the pitch cannot be made fine and significant space is required between chips
Solution Approach 1:
The patent extracts the wire bonding process entirely from the chip interconnection method. Instead of using wire bonding, the invention uses direct bonding pads on the chip surfaces that are exposed and accessible for electrical connection through the molding compound, eliminating the need for wires and the associated pitch and spacing constraints.
Solution Approach 2:
The molding compound serves as an intermediary medium that provides electrical connection pathways between stacked chips. The compound contains conductive elements or structures that enable signal transmission between bonding pads on different chips without requiring physical wire bonds, thus achieving fine pitch interconnections.
2Reliability
If significant space is maintained between adjacent semiconductor chips to prevent electrical shorts, then electrical short prevention is achieved, but the thickness of the semiconductor package increases
Solution Approach 1:
The patent removes the need for large spacing between chips by extracting the wire bonding interconnection method. The direct bonding pad exposure through the molding compound allows chips to be placed in close proximity or stacked vertically without requiring horizontal clearance, thereby reducing overall package thickness while maintaining electrical short prevention through proper insulation design.
Solution Approach 2:
The invention transitions from horizontal chip arrangement with lateral spacing to vertical stacking configuration. By stacking chips in the thickness direction and providing electrical connections through the molding compound, the design achieves high integration density without requiring significant horizontal space between adjacent chips.
3Productivity
If bonding pads are covered by stacked chips, then chip stacking density is improved, but electrical connection to bonding pads becomes difficult
Solution Approach 1:
The molding compound is applied in advance during the packaging process to encapsulate the chips and simultaneously provide exposed bonding pad structures. This preliminary action ensures that bonding pads remain accessible for electrical connection even as chips are stacked, eliminating the need for post-packaging pad exposure operations.
Solution Approach 2:
The molding compound acts as an intermediary structure that bridges the bonding pads of stacked chips. It provides conductive pathways or exposed pad surfaces that enable electrical connection through the compound, allowing high-density stacking while maintaining ease of electrical connection to all bonding pads.
Data Source
AI summary
The semiconductor package includes semiconductor chips, each chip having one or more bonding pads. The semiconductor chips are stacked in a stepped configuration over the surface of the substrate without covering one or more bonding pads. An encapsulation member encapsulates the stacked semiconductor chips on the surface of the substrate. Via wirings in the encapsulation member electrically connect to a bonding pad of at least one of the semiconductor chips. Redistributions are formed over the encapsulation member such that the one or more redistributions are electrically coupled to the via wirings.