Stepped Semiconductor Packaging for Lower Warpage and Placement Error

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Solution Overview

Problem

Wafer level chip scale packaging processes face inefficiencies and yield challenges due to the complexity of steps involved, particularly in handling and positioning semiconductor die on carriers, which can lead to warpage and placement errors.

Innovation Solution

A packaged semiconductor device with stepped sides and a contact-redistribution structure that extends laterally beyond the die, allowing for 5-side protection and improved mechanical properties, along with a method that includes partial cuts in the wafer to reduce the number of process steps and enhance handling, using encapsulating material to protect the die and facilitate optimal routing of electric signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional wafer level chip scale packaging processes are used with complete wafer singulation and carrier handling, then die can be packaged, but process complexity increases and yield decreases due to warpage and placement errors

Engineering Contradiction:
Improvepackaging yieldVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The wafer processing is segmented into two distinct cutting operations: a first cut that creates a partial separation to a first depth, and a second cut that completes the separation to a greater depth. This segmentation allows the die to remain connected during initial packaging steps, eliminating warpage issues, then separates them afterward. The redistribution structure is also segmented to extend laterally beyond the die edges, providing enhanced mechanical support.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The redistribution structure is formed and extended laterally beyond the die edges before the final separation cut is made. This preliminary action provides mechanical support to the die during handling and packaging operations, preventing warpage and placement errors. The encapsulating material is also applied in advance to protect the die surfaces before final separation.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If die are completely separated and handled individually on carriers, then packaging can proceed, but warpage and placement errors occur reducing yield

Engineering Contradiction:
Improvehandling easeVSAvoidplacement precision
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The redistribution structure is extended laterally beyond the die edges and the encapsulating material is applied to protect the die surfaces before the final separation cut. This preliminary structural reinforcement provides mechanical support during handling operations, enabling easy individual handling while preventing warpage and maintaining precise placement accuracy.

Inventive Principle:
Principle #10Preliminary action

3Strength

If redistribution structure is confined to die surface, then manufacturing is simpler, but mechanical properties and protection are insufficient

Engineering Contradiction:
Improvemechanical strengthVSAvoidmanufacturing simplicity
Core Design Contradiction:
StrengthVSEase of manufacture

Solution Approach 1:

The redistribution structure is extended laterally beyond the die edges in the horizontal dimension, creating an expanded footprint that provides enhanced mechanical support and protection. This dimensional extension strengthens the structure without adding vertical complexity, maintaining manufacturing simplicity while improving mechanical properties.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12080601B2Packaged semiconductor devices and methods therefor
Publication Date: 2024.09.03 NXP BV
  • US12080601B2 patent drawing
  • US12080601B2 patent drawing
  • US12080601B2 patent drawing

AI summary

Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.