Stepped Sidewall Dielectric Stack for Semiconductor Chip Edge Protection
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Solution Overview
Problem
Current semiconductor chip fabrication methods face challenges in increasing yield and reliability due to issues with moisture and physical cracks, as well as electrical shorts caused by metal burs, particularly in the edge regions where the scribe lane is processed.
Innovation Solution
The implementation of a semiconductor chip design featuring a substrate with a device region and edge region, where a residual test pattern and sub-pad are integrated with a stepped sidewall dielectric stack, including a passivation layer and conductive bumps, to prevent moisture and physical cracks, and a method of fabricating the chip that involves forming a preliminary hole and etching to create a stepped region, thereby reducing the risk of electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional flat sidewall dielectric stack is used, then the fabrication process is simple, but moisture ingress and physical cracks occur reducing reliability
Solution Approach 1:
The dielectric stack is segmented into multiple dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) with different materials and functions. Each layer provides specific protection against moisture ingress and physical cracks, collectively enhancing chip reliability without requiring a completely new structure.
Solution Approach 2:
The dielectric stack employs composite materials with different properties - the first dielectric layer has lower etch selectivity, the second dielectric layer has higher etch selectivity and acts as an etch stop layer, and the third dielectric layer provides additional protection. This composite structure prevents moisture ingress and physical cracks while maintaining fabrication feasibility.
2Reliability
If metal patterns are present at the breaking region, then electrical connections are established, but metal burs cause electrical shorts during mounting
Solution Approach 1:
The thick metal pattern is extracted or removed from the breaking region (scribe lane) before the sawing process. Only the necessary metal patterns in the device region are retained, eliminating the source of metal burs that would otherwise cause electrical shorts during mounting while preserving essential electrical connections.
Solution Approach 2:
The metal pattern removal is performed as a preliminary action before the sawing and mounting processes. By removing excess metal patterns in advance, the subsequent mounting process is protected from metal bur generation, preventing electrical shorts without affecting the functionality of retained metal patterns.
3Reliability
If the upper dielectric stack fully covers the residual test pattern, then protection is complete, but mounting alignment becomes difficult
Solution Approach 1:
The upper dielectric stack provides full coverage protection over the residual test pattern in terms of material layers, but the top surface is locally modified to be exposed or recessed relative to surrounding structures. This local quality difference maintains protection while creating visible alignment features for accurate mounting positioning.
Data Source
AI summary
Semiconductor chips, semiconductor packages, and semiconductor chip fabrication methods may be provided. The semiconductor chip includes a substrate including a device region and an edge region, a device layer and a wiring layer sequentially stacked on the substrate, a sub-pad on the device region and a residual test pattern on the edge region wherein a sidewall of the residual test pattern is aligned with a sidewall of the substrate, and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a portion of a top surface of the residual test pattern. A sidewall of the upper dielectric stack may have a stepped region.