Stepped Solder Mask Recesses for Low-Profile Direct Chip Attach
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing the height of conductive features to enhance strength and manufacturing costs while minimizing the risk of warping and electromigration issues.
Innovation Solution
A semiconductor device design featuring a substrate with a stepped solder mask layer, where the semiconductor die is partially positioned in a recess, reducing the height of conductive features and ensuring that only specific conductive contacts are exposed, thereby reducing the overall profile and improving adhesion of underfill material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the height of conductive features is reduced to enhance strength and reduce manufacturing costs, then the device becomes more reliable and cost-effective, but the conductive contacts may become more susceptible to warping and electromigration issues
Solution Approach 1:
The patent introduces a vertical dimension by creating recesses of different depths in the solder mask layer. This allows conductive contacts to be exposed at different heights, enabling shorter conductive features while maintaining proper electrical connections and reducing the overall profile height without compromising reliability
Solution Approach 2:
The patent applies different recess depths to different regions of the solder mask layer. First recesses have a first depth while second recesses have a second depth greater than the first depth. This localized variation allows specific conductive contacts to be exposed at appropriate heights, optimizing both strength and reliability for different connection points
2Length of stationary object
If the overall profile height is reduced to improve device compactness, then the device footprint is minimized, but the conductive features may become too short to ensure proper electrical connection
Solution Approach 1:
By utilizing vertical recesses in the solder mask layer, the patent reduces the horizontal footprint while maintaining adequate conductive feature lengths through strategic depth variation. The recesses allow the mask to be lowered only where needed, preserving connection integrity while minimizing overall profile height
3Reliability
If all conductive contacts are exposed to ensure complete electrical connectivity, then connection reliability is maximized, but the solder mask layer loses its protective function and increases device complexity
Solution Approach 1:
The patent exposes only specific conductive contacts through selectively positioned recesses rather than exposing all contacts uniformly. This localized exposure maintains the protective solder mask coverage over most of the substrate while providing necessary electrical connections, thereby reducing device complexity compared to fully exposed designs
Data Source
AI summary
Semiconductor devices, such as memory devices, and associated systems and methods, are disclosed herein. A representative semiconductor device comprises a substrate including a plurality of conductive contacts and a mask material having a surface. The mask material includes (a) a first recess formed in the surface having a first depth and (b) a second recess formed in the surface having a second depth greater than the first depth. An exposed portion of each of the conductive contacts is exposed from the mask material in the second recess. The semiconductor device further comprises a semiconductor die including a lower surface having bond pads, and the lower surface is positioned in the first recess. The semiconductor device further comprises a plurality of conductive features electrically coupling individual ones of the bond pads to corresponding ones of the exposed portions of the conductive contacts.