Stepped Source/Drain Contact Structure for Reduced Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices are scaled down to achieve higher integration density, reducing capacitance and ensuring electrical stability between contacts becomes increasingly important, but existing technologies face challenges in maintaining performance and reliability due to the decreasing pitch size.
Innovation Solution
The semiconductor device design includes specific source/drain contact structures with barrier and filling films, and gate structures that are carefully positioned and sized to enhance electrical connectivity and reduce parasitic capacitance, with the top surface of the source/drain contact being lower than the gate structure relative to the active pattern, and the source/drain barrier film extending along sidewalls and bottom surfaces of the filling film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to achieve higher integration density, then integration density is improved, but capacitance increases and electrical stability deteriorates
Solution Approach 1:
The patent applies local quality by creating different height levels for source/drain contacts relative to gate structures. Specifically, first source/drain contacts are positioned at a first height level while second source/drain contacts are positioned at a second height level that is lower than the first height level. This localized variation in contact height allows optimization of electrical properties in different regions of the device, reducing parasitic capacitance between contacts and gate structures while maintaining high integration density.
2Productivity
If pitch size decreases to increase integration density, then integration density is improved, but capacitance between contacts increases
Solution Approach 1:
The patent employs dimensionality change by transitioning from a planar contact structure to a multi-level three-dimensional contact structure. By positioning source/drain contacts at different height levels (first height level and second height level), the invention utilizes the vertical dimension to separate contacts that would otherwise be in close proximity in the horizontal plane. This vertical separation effectively reduces parasitic capacitance between contacts while maintaining small pitch sizes for high integration density.
3Reliability
If source/drain contact height is increased to improve electrical connectivity, then electrical conductivity is improved, but damage during etching increases
Solution Approach 1:
The patent applies segmentation by dividing the source/drain contact structure into multiple segments at different height levels. Instead of creating a single tall contact that would be susceptible to etching damage, the structure is segmented into first source/drain contacts at a first height level and second source/drain contacts at a second height level. This segmentation reduces the height of individual contact segments, thereby minimizing etching damage while maintaining overall electrical connectivity through the multi-level configuration.
Data Source
AI summary
A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.