Stepped Source-Drain Contacts for Low-Resistance GAA Transistors
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Solution Overview
Problem
Conventional gate-all-around transistor structures face challenges due to high resistance caused by large source drain epitaxy regions and small contact areas between channel ends and source drain epitaxy, limiting device performance and integration density.
Innovation Solution
The proposed solution involves a gate-all-around transistor structure with stepped source drain contacts, where salicide regions are formed from exposed ends of nanosheet channel regions, allowing for direct contact and reducing resistance, and a gate conductor surrounds the channel regions on three sides, enabling efficient current transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large source drain epitaxy regions are used, then device area is increased, but parasitic resistance increases and device performance deteriorates
Solution Approach 1:
The source and drain regions are segmented into multiple discrete salicide regions, each corresponding to a specific channel region. This segmentation allows each contact to be precisely positioned and sized, reducing parasitic resistance while maintaining compact device area. The segmented approach enables independent optimization of each contact region rather than using a single large epitaxy region.
Solution Approach 2:
The patent implements local quality by creating salicide regions with specific properties at precise locations adjacent to channel regions. Each salicide region is formed with controlled dimensions and material composition tailored to its specific position, optimizing electrical contact properties locally rather than using uniform source drain regions throughout the device.
2Area of stationary object
If small contact areas between channel ends and source drain epitaxy are used, then device area is reduced, but contact resistance increases
Solution Approach 1:
The contact structure is segmented into multiple discrete salicide regions, each providing a dedicated contact area between the channel and source/drain regions. This segmentation enables precise control of contact area dimensions, ensuring sufficient contact area for low resistance while maintaining overall compact device footprint through optimized spacing and positioning of individual contacts.
Solution Approach 2:
The patent applies parameter changes by controlling the dimensions, shape, and material composition of salicide regions to optimize contact properties. The salicide formation process allows precise adjustment of contact area parameters such as width, length, and depth, enabling minimization of contact resistance while maintaining small device area through optimized geometric parameters.
3Ease of manufacture
If conventional source drain contacts are used, then manufacturing process is simple, but parasitic resistance is high and integration density is limited
Solution Approach 1:
The contact formation process is segmented into discrete salicide region formation steps, allowing independent patterning and formation of each contact region. This segmentation enables higher integration density by allowing precise positioning of multiple contacts within compact areas while maintaining manufacturing simplicity through standardized salicide formation processes that can be applied repeatedly across different contact locations.
Solution Approach 2:
The patent utilizes another dimension by forming salicide regions that extend in multiple spatial dimensions adjacent to channel regions. The salicide structures can be formed with controlled depth, width, and lateral extent, utilizing three-dimensional space more efficiently to create multiple contact regions without increasing planar device area, thereby increasing integration density while maintaining process simplicity.
Data Source
AI summary
A gate-all-around transistor structure including a channel region surrounded on three sides by a gate conductor, and a pair of salicide regions extending from opposite ends of the channel region in a direction parallel with the gate conductor.