Stepped-source LDMOS architecture for breakdown voltage
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Solution Overview
Problem
Existing semiconductor devices, such as power MOSFETs, face limitations in fabrication complexity and electrical performance due to the use of buried p-type regions and non-self-aligned drift regions, which increase the likelihood of drain-to-source punch-through and reduce breakdown voltage.
Innovation Solution
The semiconductor device incorporates a self-aligned drift region with shallow and deep portions of different doping concentrations, where the shallow portion has a higher peak doping concentration and the deep portion has a lower peak doping concentration, vertically separated by a region of opposite conductivity type, allowing for improved control over gate-to-source and gate-to-drain capacitances and increased breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If buried p-type regions and non-self-aligned drift regions are used in power MOSFETs, then fabrication can be simplified, but drain-to-source punch-through increases and breakdown voltage decreases
Solution Approach 1:
The drift region is segmented into shallow and deep portions with different doping concentrations. The shallow portion has higher peak doping concentration while the deep portion has lower peak doping concentration, creating a stepped profile that reduces punch-through while maintaining fabrication simplicity
Solution Approach 2:
The invention transitions from a planar, non-self-aligned drift region to a vertically stratified structure with shallow and deep portions at different depths. This vertical dimensionality allows the drift region to be self-aligned with the gate, improving breakdown voltage without complicating fabrication
2Ease of manufacture
If buried p-type regions and non-self-aligned drift regions are used in power MOSFETs, then fabrication can be simplified, but drain-to-source punch-through increases
Solution Approach 1:
The drift region is divided into shallow and deep portions with different doping concentrations. The shallow portion extends closer to the surface with higher doping to prevent punch-through, while the deep portion provides bulk support, collectively reducing drain-to-source punch-through risk
Solution Approach 2:
The drift region is configured to be self-aligned with the gate structure, eliminating the need for separate alignment steps. The shallow and deep portions work together autonomously to prevent punch-through through their combined doping profiles and spatial arrangement
3Device complexity
If conventional source region structure is used, then fabrication is simpler, but gate-to-source and gate-to-drain capacitances are higher
Solution Approach 1:
The source region is segmented into first, second, and third portions with different conductivity types and depths. The second portion penetrates deeper than the third but not as deep as the first, creating a stepped configuration that reduces overlapping areas with the gate, thereby reducing gate-to-source and gate-to-drain capacitances
Solution Approach 2:
The source region transitions from a conventional single-layer structure to a multi-level stepped structure with portions at different depths. This vertical stratification reduces lateral overlap with the gate electrode, effectively reducing parasitic capacitances without significantly increasing fabrication complexity
Data Source
AI summary
A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.