Stepped Stack Openings to Prevent Fill Cracks in Vertical Memory
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Solution Overview
Problem
During the fabrication of vertical memory arrays, the fill material in large openings undergoes stress and shrinkage, leading to cracking and delamination, which becomes more pronounced as the number of tiers increases.
Innovation Solution
The introduction of a stepped profile along the sidewalls of the stack opening, formed through a 'trim-etch-trim' process, prevents cracks from forming or propagating in the fill material, even under stress from thermal treatment and planarization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large opening is formed in tiers to increase memory density, then the memory density is improved, but the fill material is subjected to stress and shrinkage causing cracking and delamination
Solution Approach 1:
The sidewalls of the tiers are segmented into multiple sections with varying thicknesses, creating a stepped profile. This segmentation reduces the continuous stress path in the fill material, preventing crack propagation while maintaining the large opening structure needed for high memory density.
Solution Approach 2:
Different sections of the sidewalls have different thicknesses, creating local variations in structural properties. The thinner sections reduce stress concentration points where cracks would otherwise initiate and propagate, while the overall structure maintains sufficient strength to support the high-density configuration.
2Manufacturing precision
If thermal treatment and abrasive planarization are applied to densify and planarize the fill material, then the fill material density and surface flatness are improved, but mechanical stress causes cracking and delamination
Solution Approach 1:
The stepped profile segments the sidewalls into multiple thickness sections, which interrupts the continuous stress path that would otherwise form during thermal treatment and planarization. This segmentation prevents stress concentration and crack initiation, allowing the fill material to undergo densification and planarization without compromising integrity.
Solution Approach 2:
By creating local variations in sidewall thickness, the structure provides different mechanical properties at different locations. The thinner sections specifically target stress concentration zones, reducing the likelihood of cracking during stress-intensive processes like thermal treatment and CMP, while still achieving the required surface planarity.
3Productivity
If the number of tiers is increased to increase memory density, then the memory density is improved, but cracking and delamination of the fill material becomes more problematic
Solution Approach 1:
As the number of tiers increases, the stepped profile with multiple thickness sections creates multiple discontinuities in the stress path. Each step acts as a stress relief point, preventing cracks from propagating continuously through the entire fill material height, thereby enabling higher tier counts without proportionally increasing crack risk.
Solution Approach 2:
The varied thickness sections create local mechanical property differences that specifically address stress concentration issues. This allows the structure to accommodate increased tier density while the local thickness variations continuously interrupt potential crack paths, preventing the linear increase in crack propagation risk that would otherwise occur with more tiers.
Data Source
AI summary
A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.