Stepped Stack Semiconductor Device with Spacer Patterning
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Solution Overview
Problem
The increasing number of stacked word lines in three-dimensional memory devices leads to a surge in connecting lines, which is difficult to manage due to size limitations, resulting in higher manufacturing costs and the need for additional mask processes.
Innovation Solution
The implementation of stepped stack structures with conductive patterns that are separated by slits and arranged in a specific direction, allowing for the formation of connecting lines and contact pads using spacer patterning technology (SPT), reducing the number of mask processes and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked word lines is increased to improve integration, then memory capacity is improved, but the number of connecting lines increases making the device difficult to manage and increasing manufacturing cost
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture. Word lines are stacked vertically in multiple layers (first through fourth word lines in different layers), allowing increased memory capacity within the same footprint. Connecting lines are also arranged in multiple layers to accommodate the increased number of word lines, effectively managing complexity through vertical dimension utilization.
Solution Approach 2:
The memory device is divided into multiple functional layers with word lines segmented into first through fourth layers, each containing specific word lines (W0-W7). Connecting lines are also segmented into multiple layers (first connecting lines in first layer, second connecting lines in second layer), allowing independent routing and management of different signal paths, thus reducing overall system complexity.
2Quantity of substance
If the number of conductive layers is increased to accommodate more connecting lines, then the number of connecting lines is increased, but the number of mask processes increases leading to higher manufacturing cost
Solution Approach 1:
Multiple connecting lines are merged into common conductive layers. The first connecting lines (CL0-CL7) are formed in the first conductive layer, and the second connecting lines (CL0-CL7) are formed in the second conductive layer, with each layer serving multiple word lines simultaneously. This merging approach allows numerous connecting lines to be accommodated without proportionally increasing mask processes, as each mask process creates patterns that serve multiple functions.
Solution Approach 2:
The conductive layers are designed with multi-functionality where the same layer structure and formation process serve multiple purposes. The first and second conductive layers each contain multiple connecting lines that can connect to different word lines, making these layers universal connectors rather than dedicated single-purpose lines, thereby reducing the total number of distinct manufacturing steps required.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming stepped stack structures each including conductive patterns stacked in a shape of steps while exposing respective ends thereof and surrounding channel layers, the stepped stack structures being separated from one another by slits, forming first and second contact plugs connected to the ends of the conductive patterns to extend along an extending direction of the channel layers, and simultaneously forming, using a spacer patterning technology (SPT), bit lines connected to one or more of the channel layers and extending along a first direction, first connecting lines extending along a second direction intersecting the first direction, and contact pads extending from the first connecting lines to be connected to the first contact plugs.