Stepped Substack Interlayer Connectors for 3D ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the number of layers in high-density memory devices increases, the complexity and cost of manufacturing interlayer connectors rise due to the need for multiple lithographic steps and deeper vias, leading to process control issues and increased layout area.
Innovation Solution
A stepped substack interlayer connector structure is introduced, where conductors form connections in respective regions with a maximum depth equal to or less than the thickness of one substack, reducing the number of lithographic steps and via depths by using a staircase configuration of active and insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in high-density memory devices is increased, then storage density is improved, but the complexity and cost of manufacturing interlayer connectors increases
Solution Approach 1:
The patent divides the stack of active layers into multiple substacks, where each substack contains a subset of the active layers. Interlayer connectors are formed separately for each substack, allowing the manufacturing process to be segmented into manageable units. This segmentation reduces the overall complexity by breaking down the formation of connectors to all layers into multiple simpler operations, each handling only a portion of the total layers.
Solution Approach 2:
The patent introduces a lateral dimension to the connector formation process by forming connectors for different substacks at different lateral positions. Instead of forming all connectors in a single vertical operation, the process utilizes lateral separation to organize connector formation, effectively adding a spatial dimension to the manufacturing approach and reducing process complexity.
2Manufacturing precision
If multiple lithographic steps are used to form interlayer connectors, then connection precision is improved, but manufacturing cost and process time increase
Solution Approach 1:
The patent combines the formation of multiple interlayer connectors into a single lithographic step by laterally separating the substacks. Instead of performing sequential lithography operations for each connector, all connectors are formed simultaneously in one step, significantly reducing the total number of lithographic steps required while maintaining precision through the lateral separation strategy.
3Adaptability or versatility
If via depth is increased to reach deeper layers, then connectivity to lower layers is improved, but process control difficulty and layout area increase
Solution Approach 1:
The patent segments the vertical connectivity requirement into multiple shallower connections by dividing layers into substacks. Each interlayer connector only needs to traverse the thickness of one substack rather than the entire stack, resulting in significantly reduced via depths. This segmentation makes the etching and filling processes more controllable and reduces the layout area required for connector access.
Data Source
AI summary
A stepped substack interlayer connector structure on a multilayer integrated circuit includes N steps on the substrate from a surface of the substrate at a first level to a surface of the substrate at a second level. A stack of active layers alternating with insulating layers on the substrate, including a plurality of substacks disposed in relation to the N step(s) to form respective contact regions in which the substacks are disposed at a common level. Interlayer connectors are formed by conductors in the respective regions connected to landing areas on active layers in each of the plurality of substacks. The maximum depth of the interlayer connectors is equal to, or less than, the thickness of one of the substacks.