Stepped Substrate Multichip Package for EMIB Elimination
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Solution Overview
Problem
Multichip electronic packages with embedded multi-die interconnect bridges (EMIB) suffer from non-optimal package form factor and increased power consumption due to the need for large X-Y footprints and electrical path losses, particularly in photonic systems where signal transmission across EMIBs results in inefficiencies.
Innovation Solution
A multichip electronic package with a stepped top surface substrate architecture, where dies are directly connected without the need for EMIBs, reducing footprint and power consumption by using a package substrate with multiple plateaus and direct interconnects between dies, eliminating the requirement for bridge substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EMIB architecture is used to interconnect multichip heterogeneous integration, then high density interconnects between components are achieved, but package footprint and power consumption increase
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D stacked architecture where dies are vertically positioned at different heights on the substrate. This dimensional change allows high-density interconnects without increasing the lateral footprint, as components are arranged in multiple vertical layers rather than spread out horizontally.
Solution Approach 2:
The patent introduces through-substrate vias as intermediary conductive pathways that penetrate the substrate vertically. These vias serve as mediators enabling direct electrical connection between dies at different vertical levels, eliminating the need for lateral EMIB routing and reducing both footprint and power consumption.
2Reliability
If EMIB architecture is used to interconnect multichip heterogeneous integration, then high density interconnects between components are achieved, but power consumption increases due to electrical path losses
Solution Approach 1:
By routing interconnects vertically through the substrate rather than laterally across EMIBs, the patent shortens the electrical path length. This dimensional reconfiguration reduces resistive losses and power consumption while maintaining high interconnect density.
Solution Approach 2:
Through-substrate vias act as efficient intermediary conductors with low resistance, providing direct vertical electrical pathways between dies. This eliminates the need for high-power-consuming lateral EMIB paths while achieving dense interconnects.
3Reliability
If components are laterally adjacent with EMIR stitching, then interconnection is achieved, but large X-Y footprint is required
Solution Approach 1:
The patent eliminates lateral adjacency requirements by stacking dies vertically. Through-substrate vias provide interconnection in the vertical dimension, freeing up lateral space and dramatically reducing the X-Y footprint while maintaining full interconnectivity.
Data Source
AI summary
Embodiments disclosed herein include electronic packages and methods of assembling an electronic package. In an embodiment, an electronic package comprises a package substrate with a stepped top surface, and a first die on a first plateau of the stepped top surface. In an embodiment, a second die is on a second plateau of the stepped top surface, where the second die extends over the first die, In an embodiment, a third die is on a third plateau of the stepped top surface, where the third die extends over the second die.