Stepped Substrate Semiconductor Package for Compact Integration
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Solution Overview
Problem
Current semiconductor packages face challenges in integrating multiple semiconductor chips and peripheral components in a compact form without increasing thickness, while maintaining high performance and data transfer rates.
Innovation Solution
The semiconductor package design features a substrate with distinct height levels, where the upper semiconductor chip overlaps the substrate and is connected via flip-chip interconnections, with additional semiconductor chips stacked via through-silicon-vias (TSVs), and peripheral components embedded in a mold layer, allowing for a compact structure with improved signal transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips and peripheral components are integrated in a single package, then functionality and data transfer rates are improved, but package thickness increases
Solution Approach 1:
The substrate is designed with a first part and a second part at different height levels, creating a stepped configuration. This dimensional variation allows electronic components to be positioned in the space between the second part of the substrate and the first semiconductor chip, enabling vertical integration without increasing overall package thickness.
Solution Approach 2:
Electronic components are embedded within the mold layer in the space created by the stepped substrate structure. This nesting approach places components within the existing package volume rather than adding to the external dimensions, allowing multiple chips and components to coexist in a compact arrangement.
2Adaptability or versatility
If multiple semiconductor chips are stacked to increase functionality, then device complexity increases
Solution Approach 1:
The package is segmented into distinct functional regions: the first part of the substrate at a higher level for the first semiconductor chip, the second part at a lower level for electronic components, and additional semiconductor chips stacked via TSVs. This segmentation organizes multiple chips and components into manageable sections with clear functional assignments, reducing overall system complexity.
3Area of stationary object
If the substrate area is reduced to minimize package size, then manufacturing precision requirements increase
Solution Approach 1:
The substrate employs an asymmetric stepped design with the first part extending further than the second part. This asymmetric configuration optimizes the use of substrate area by placing the largest components (first semiconductor chip) over the largest area (first part), while smaller electronic components are positioned in the space under the overhang, reducing overall substrate area requirements without compromising component placement precision.
Data Source
AI summary
A semiconductor device includes a substrate having a first part and a second part, the first and second parts being continuous with each other and at different height levels, a first semiconductor chip overlapping the first and second parts of the substrate, an electrical interconnection structure connecting the first part of the substrate and the first semiconductor chip, a distance between the first part of the substrate and the first semiconductor chip being shorter than a distance between the second part of the substrate and the first semiconductor chip, and at least one electronic component in a space between the second part of the substrate and the first semiconductor chip.