Stepped External Terminal Layout for High-Voltage Insulation
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Solution Overview
Problem
Conventional semiconductor devices experience insulation failure due to high electric field concentration at the connection points of external terminals when high voltage is applied for extended periods, leading to deterioration of insulating members.
Innovation Solution
The semiconductor device incorporates a laminated structure of external terminals with an insulating sheet disposed between them, where the rear surface of one terminal is angled to increase the distance between the terminals as the end is approached, reducing electric field concentration through a staircase pattern and rounded or chamfered end portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If external terminals are connected closely to reduce device size, then device compactness is improved, but electric field concentration increases causing insulation failure
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stepped configuration. The first external terminal is positioned at a higher level than the second external terminal, creating vertical separation in addition to horizontal spacing. This dimensional change allows compact planar footprint while maintaining adequate electric field isolation through vertical distance.
Solution Approach 2:
The patent applies rounded end portions to the external terminals instead of sharp edges. This curvature treatment distributes the electric field more evenly across the terminal surfaces, preventing concentration at sharp corners and reducing the risk of insulation breakdown while maintaining compact dimensions.
2Reliability
If creepage distances are increased to reduce electric field concentration, then insulation performance is improved, but device area increases
Solution Approach 1:
The patent utilizes the vertical dimension to achieve creepage distance requirements without increasing planar area. By stacking external terminals at different heights, the effective creepage path is extended in the vertical direction while maintaining a compact footprint on the substrate.
Solution Approach 2:
Rounded end portions reduce electric field concentration at terminal edges, allowing smaller creepage distances to achieve the same insulation performance as larger distances with sharp edges. This enables compact device area while maintaining required insulation levels.
3Reliability
If insulating material with lower dielectric constant is injected to reduce electric field, then insulation performance is improved, but device complexity increases
Solution Approach 1:
The patent uses geometric modification (rounded ends) as a simpler alternative to material injection. By changing the shape of terminal ends, electric field concentration is reduced without requiring additional manufacturing steps for injecting specialized insulating materials, thus avoiding increased device complexity.
Data Source
AI summary
A semiconductor device includes a terminal portion including a second external terminal, an insulating sheet disposed on the second external terminal, and a first external terminal disposed on the insulating sheet. The first external terminal has a first end portion with a first end. At the first end portion, a rear surface of the first external terminal is not parallel to a front surface of the second external terminal so that, in a thickness direction of the first external terminal, a distance between the first external terminal and the second external terminal increases with as the first end is approached.