Stepped Terrace Chip Package Assembly Reduces Vertical Error
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Solution Overview
Problem
Existing assembly techniques for stacked semiconductor chip packages are time-consuming and have low yields, leading to significant vertical position errors and increased costs due to tight manufacturing tolerances and limited chip stacking capabilities.
Innovation Solution
The use of an assembly component with a stepped terrace that offsets semiconductor dies in a horizontal direction, allowing for independent referencing to an assembly component rather than the preceding die, which reduces cumulative vertical position errors and facilitates high-throughput, low-cost manufacturing of high-performance chip packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing assembly techniques are used to stack semiconductor chips, then chip packages can be assembled, but the total vertical position error becomes prohibitively large due to cumulative errors from each chip
Solution Approach 1:
The patent divides the stack into segments with intermediate support structures (such as substrate layers or support chips) that provide reference planes. Each segment's vertical position is independently controlled relative to its support structure, preventing cumulative errors from propagating through the entire stack. This segmentation allows more chips to be stacked while maintaining manufacturing precision.
2Manufacturing precision
If tight manufacturing tolerances are applied to reduce individual vertical position errors, then manufacturing precision improves, but cost increases
Solution Approach 1:
The patent introduces intermediate support structures (substrate layers, support chips, or adhesive layers with controlled thickness) that act as mediators between chips. These intermediaries provide stable reference planes and absorb dimensional variations, allowing chips to be assembled with relaxed tolerances while maintaining overall stack precision, thereby reducing manufacturing cost.
3Adaptability or versatility
If more semiconductor chips are stacked to increase performance, then system performance improves, but total vertical position error becomes prohibitively large
Solution Approach 1:
By segmenting the stack with intermediate support structures, the patent enables assembly of more chips (increasing performance) while each segment's position is independently controlled. The support structures break the cumulative error chain, allowing high chip counts without prohibitively large total vertical position errors.
4Productivity
If existing assembly techniques are used, then chip packages can be assembled, but assembly time is excessive and yields are low
Solution Approach 1:
The patent employs preliminary alignment features (such as pre-formed adhesive layers with controlled thickness, pre-positioned support structures, or pre-aligned reference markers) that enable rapid and accurate chip placement. This preliminary preparation eliminates time-consuming iterative alignment processes, increasing assembly throughput and yield while reducing assembly time.
Data Source
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AI summary
An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terraced at one side of the vertical stack. The chip package may be assembled using the assembly component. The assembly component may include a housing having another stepped terrace. This other stepped terrace may include a sequence of steps in the vertical direction, which are offset from each other in the horizontal direction. Furthermore, the housing may be configured to mate with the set of semiconductor dies such that the set of semiconductor dies are arranged in the stack in the vertical direction. For example, the other stepped terrace may approximately be a mirror image of the stepped terrace.