Semiconductor Memory Terrace Interconnects for Reliable 3D Coupling
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently integrating and scaling memory capacity while maintaining reliable electrical connections and structural integrity, particularly in three-dimensional memory structures.
Innovation Solution
The semiconductor memory device employs a novel interconnect layer configuration with stepped terrace portions and insulated connections, including first, second, and third terrace portions, to enhance electrical coupling and structural stability, utilizing a first memory pillar and contact that extend through multiple interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is adopted to increase integration and capacity, then storage density is improved, but structural integrity and electrical connection reliability deteriorate
Solution Approach 1:
The interconnect structure is divided into multiple discrete layers (first interconnect layer, second interconnect layers, third interconnect layers) with distinct functional regions. Each layer is segmented into specific portions (first terrace portions, second terrace portions, third terrace portions) that can be independently formed and controlled, allowing for reliable electrical connections at each level while maintaining overall three-dimensional integration.
Solution Approach 2:
The patent transitions from planar interconnect structures to three-dimensional stepped terrace structures. The interconnect layers are arranged in multiple vertical levels with horizontal terraces, creating a multi-dimensional configuration that increases storage density while maintaining electrical connection reliability through vertical stacking and lateral coupling pathways.
2Quantity of substance
If interconnect layers are stacked to increase capacity, then integration is improved, but manufacturing complexity increases
Solution Approach 1:
The complex interconnect structure is divided into manageable segments: first interconnect layers forming first terrace portions, second interconnect layers forming second terrace portions, and third interconnect layers forming third terrace portions. Each segment can be manufactured using similar processes, reducing overall manufacturing complexity despite the multi-layer integration.
Solution Approach 2:
The interconnect structure employs a nested configuration where first terrace portions are positioned at lower levels, second terrace portions are positioned at intermediate levels, and third terrace portions are positioned at upper levels. This nested arrangement allows for systematic manufacturing where each layer can be formed and integrated in a sequential manner, managing complexity through hierarchical organization.
3Strength
If terrace portions are made thicker to improve structural integrity, then structural stability is improved, but electrical coupling efficiency deteriorates
Solution Approach 1:
Different portions of the interconnect structure have different thickness characteristics optimized for their specific functions. The terrace portions have increased thickness for structural stability and mechanical support, while the coupling portions between layers maintain appropriate thickness for efficient electrical coupling. This local differentiation allows simultaneous optimization of both structural integrity and electrical performance.
Solution Approach 2:
The interconnect structure utilizes composite material configurations where conductive materials are combined with insulating materials in specific patterns. The terrace portions employ thicker conductive layers for structural support, while coupling regions use optimized material compositions and configurations to ensure efficient electrical coupling between layers, balancing mechanical and electrical requirements.
Data Source
AI summary
In general, according to one embodiment, a semiconductor memory device includes: a plurality of second and third interconnect layers apart from each other in a first direction, wherein each of the second interconnect layers includes a plurality of first terrace portions, each of the third interconnect layers includes a plurality of second terrace portions overlapping the first terrace portions in the first direction, the second terrace portions include a plurality of third and fourth terrace portions provided at a same interconnect layer of the third interconnect layers are electrically insulated from each other; and a first contact passes through one of the fourth terrace portions, and is electrically coupled to one of the first terrace portions, wherein each of the third and fourth terrace portions is thicker in the first direction than a portion of the third interconnect layers where the third or fourth terrace portions are not provided.