Stepped Trench Gate HEMT Structure for DIBL Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-electron-mobility transistors (HEMTs) of the normally on type face the issue of drain-induced barrier lowering (DIBL) phenomenon, leading to premature turning-on and high leakage currents at low drain-to-source voltages, which is undesirable in enrichment mode operation.
Innovation Solution
A HEMT transistor design featuring a semiconductor heterostructure with a trench and a conductive gate region coated by a dielectric material, where the trench is laterally delimited by a lateral structure forming a step, reducing the electrical field and mitigating the DIBL effect by distributing it more evenly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a HEMT transistor is designed with a conventional gate structure, then the device can operate in normally on mode, but it suffers from DIBL phenomenon causing high leakage currents and premature turning-on
Solution Approach 1:
The gate structure is segmented into multiple regions at different depths within the trench. The gate electrode is divided into a first gate region extending into the AlGaN layer and a second gate region extending into the GaN layer, with each region providing independent electrical control. This segmentation allows the electric field to be distributed and controlled at different depths, preventing the concentration of field lines that causes DIBL phenomenon and reducing leakage currents.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional trench gate structure. The gate electrode extends vertically into the semiconductor layers, creating a depth dimension that enables better electric field control. This dimensional change allows the gate to exert control over the channel at multiple depth levels, effectively suppressing the DIBL effect that occurs in conventional planar structures.
2Reliability
If the trench gate structure is implemented, then the DIBL phenomenon is prevented and leakage current is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming the trench structure, depositing the gate electrode material, and creating the dielectric region. Each stage is independently optimized and can be performed using standard semiconductor fabrication techniques. The segmentation of both the gate electrode and the manufacturing process reduces overall complexity by breaking down the complex trench gate formation into manageable, sequential steps.
3Ease of operation
If the gate region extends deeply into the semiconductor layers, then control over the channel is improved, but the electrical field concentration increases causing DIBL effect
Solution Approach 1:
The gate electrode is segmented into multiple regions at different depths, with the first gate region in the AlGaN layer and the second gate region in the GaN layer. This segmentation distributes the electrical field control function across multiple depth levels, maintaining strong channel control while preventing field concentration at any single location. Each gate region contributes to overall channel modulation without creating the field concentration that triggers DIBL.
Solution Approach 2:
The dielectric region is configured to create equipotential surfaces that distribute the electrical field uniformly across the channel. By ensuring that the dielectric material provides consistent electrical potential distribution, the structure prevents localized field concentration while maintaining effective gate control over the channel, thereby suppressing DIBL phenomenon.
Data Source
AI summary
A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.