Stepped Trench MOSFET Gate Structure for Lower Field Stress
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Solution Overview
Problem
Trench MOSFETs face reliability issues due to excessively high electric fields at the gate bottom, which are not adequately addressed by existing manufacturing methods.
Innovation Solution
A self-align multi trench MOSFET manufacturing method that forms trenches with stepped sidewalls, incorporating a gate dielectric layer and barrier layer to reduce the electric field and enhance device reliability, while reducing on-resistance through a self-aligned process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a trench structure is used to reduce on-resistance, then power density increases, but the electric field at the gate bottom becomes excessively high reducing reliability
Solution Approach 1:
The gate structure is segmented into multiple levels with different widths. The gate has a first gate width at the top and a second gate width at the bottom, where the second gate width is greater than the first. This segmentation allows the electric field to be distributed more evenly, reducing the peak electric field density at the gate bottom while maintaining the trench structure's low on-resistance characteristic.
Solution Approach 2:
Different regions of the gate are given different local properties. The gate width is locally increased at the bottom portion compared to the top portion, creating a non-uniform gate structure. This local quality change specifically addresses the high electric field problem at the gate bottom without affecting the overall trench structure's power density benefits.
2Power
If the gate width is increased to reduce on-resistance, then conduction current increases, but the electric field concentration at the gate bottom worsens
Solution Approach 1:
The gate width is segmented into two distinct portions: a first gate width at the top and a second gate width at the bottom. The second gate width is deliberately made greater than the first gate width. This segmentation enables the gate to provide lower on-resistance through increased effective width while simultaneously reducing electric field concentration at the bottom by distributing the field over a larger area.
Solution Approach 2:
The gate structure transitions from a uniform two-dimensional cross-section to a three-dimensional structure with varying width along its length. By introducing the dimension of vertical width variation, the gate can simultaneously achieve low resistance (through increased effective area) and reduced field concentration (through distributed geometry).
Data Source
AI summary
A manufacturing method of a self-align multi trench MOSFET includes forming an epitaxial layer on a substrate, forming a deep well region in the epitaxial layer, and forming a first conductive type heavily doped region in the deep well region on the surface of the epitaxial layer. A patterned hard mask is formed on the surface of the epitaxial layer to expose a portion of the epitaxial layer. A multiple trench formation process is performed to form trenches with stepped sidewalls in the epitaxial layer. Each process within the multiple trench formation process includes etching the exposed epitaxial layer and trimming the patterned hard mask to expose the surface of the epitaxial layer. After the multiple trench formation process, the patterned hard mask is removed. A gate dielectric layer is formed above the bottoms and stepped sidewalls of the trenches, and a gate is formed in the trenches.