Stepped Through-Silicon Via Layout for Precise BEOL Landing
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Solution Overview
Problem
The challenge in semiconductor manufacturing is accurately landing a through silicon via (TSV) on a landing pad at the metal level of the back-end-of-line (BEOL) due to the large depth of the TSV, leading to larger vias that occupy more space and risk short circuits with nearby transistors.
Innovation Solution
The solution involves creating guiding pads aligned with the landing pad and using a discontinuous width increase in the TSV to ensure precise alignment and landing, with the TSV having a first portion that aligns with the guiding pads and a second portion that widens to accommodate the landing pad, thereby reducing the risk of shorts and optimizing space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a larger through via is used to ensure accurate landing on the landing pad, then the reliability of connection is improved, but the area occupied increases and the risk of short circuit with nearby transistors increases
Solution Approach 1:
The via structure employs different widths at different vertical levels: a first width at the landing pad level for reliable connection, and a second (smaller) width at the bump electrode level to reduce area occupation. This local differentiation allows the via to simultaneously achieve reliable landing connection and minimize space usage and short circuit risk.
Solution Approach 2:
The via is divided into distinct segments with different cross-sectional dimensions - a first via portion with a first width and a second via portion with a second width. This segmentation enables each portion to be optimized for its specific function: the lower portion for reliable landing and the upper portion for space efficiency.
2Reliability
If a larger through via is used to ensure accurate landing on the landing pad, then the reliability of connection is improved, but the device complexity increases due to additional space requirements
Solution Approach 1:
The via structure employs different widths at different vertical levels: a first width at the landing pad level for reliable connection, and a second (smaller) width at the bump electrode level to reduce area occupation. This local differentiation allows the via to simultaneously achieve reliable landing connection and minimize space usage and short circuit risk.
3Manufacturing precision
If the through via depth is reduced to simplify manufacturing, then the manufacturing precision requirement is improved, but the connection reliability between BSPDN and BEOL deteriorates
Solution Approach 1:
The via structure employs different widths at different vertical levels: a first width at the landing pad level for reliable connection, and a second (smaller) width at the bump electrode level to reduce area occupation. This local differentiation allows the via to simultaneously achieve reliable landing connection and minimize space usage and short circuit risk.
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a landing pad in a back-end-of-line structure; a backside power distribution network in a backside dielectric layer; and a through silicon via extending from the backside dielectric layer to the landing pad in the back-end-of-line structure, where the through silicon via has a first portion of a first width and a second portion of a second width and a discontinuous increase in width from the first width of the first portion to the second width of the second portion. A method of forming the same is also provided.