Stepped Conductive Via Structure to Prevent Bridging
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Solution Overview
Problem
The manufacturing of miniaturized semiconductor devices faces challenges such as poor electrical interconnection, misalignment of components, and increased complexity, leading to yield loss and higher manufacturing costs due to the complexity of operations on small and thin semiconductor devices.
Innovation Solution
A semiconductor structure is designed with a first conductive member surrounded by a first dielectric layer, and a second conductive member with a first portion and a second portion disposed over the first portion, surrounded by different dielectric layers, creating a step contour to increase clearance between conductive members, preventing undesirable contact and improving alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If miniaturized semiconductor devices are manufactured with more different small components, then device functionality and integration are improved, but manufacturing complexity increases leading to poor electrical interconnection and misalignment
Solution Approach 1:
The patent segments the conductive via structure into multiple portions (first conductive via portion, second conductive via portion) surrounded by different dielectric layers. This segmentation allows independent formation and alignment of each conductive portion, reducing manufacturing complexity while maintaining device functionality through modular construction
Solution Approach 2:
The patent introduces a vertical dimension by forming conductive vias that extend through multiple dielectric layers at different depths. The first conductive via portion extends from a first surface through a first dielectric layer, while the second conductive via portion extends from a second surface through a second dielectric layer, enabling three-dimensional interconnection that resolves alignment issues in miniaturized devices
2Volume of moving object
If conductive vias are formed closer together to reduce device size, then miniaturization is achieved, but bridging between conductive vias occurs reducing reliability
Solution Approach 1:
The conductive via structure is divided into separate portions surrounded by different dielectric layers, creating physical and electrical isolation between adjacent vias. This segmentation prevents bridging while allowing closer spacing of vias, enabling miniaturization without compromising reliability
Solution Approach 2:
Different dielectric layers act as intermediary materials between adjacent conductive via portions. These dielectric layers provide electrical isolation and mechanical support, preventing direct contact (bridging) between conductive vias while maintaining structural integrity at reduced dimensions
3Adaptability or versatility
If manufacturing operations are increased to accommodate more components, then device integration is improved, but yield loss increases due to alignment issues
Solution Approach 1:
The patent segments the conductive interconnection structure into multiple independently formable portions, each surrounded by its own dielectric layer. This segmentation simplifies the manufacturing process for highly integrated devices by allowing step-by-step formation of conductive structures, improving alignment and reducing yield loss
Solution Approach 2:
The patent employs preliminary formation of dielectric layers and conductive via portions in a structured sequence. By pre-forming dielectric layers and conductive portions in controlled steps, the patent enables better alignment and reduces manufacturing defects, thereby improving yield for highly integrated devices
Data Source
AI summary
A semiconductor structure includes a first conductive member, a second conductive member and a third conductive member. The first conductive member is extended through and is laterally surrounded by a first dielectric layer. The second conductive member is disposed over the first dielectric layer and the first conductive member, and is laterally surrounded by a second dielectric layer. The third conductive member is disposed over the second conductive member, and is laterally surrounded by the second dielectric layer, wherein a portion of the second conductive member is protruded into the third conductive member.