Stepped Via Insulating Layer for TFT Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional LCD devices face challenges with TFT stability due to sensitivity to light, water, and oxygen, leading to reduced efficiency and display quality over time, especially with polycrystalline and amorphous TFTs, and the need for protection layers that do not fully mitigate these issues.
Innovation Solution
A display panel design featuring a TFT substrate with a first and second insulating sub-layer on the drain, forming a stepped via for the pixel electrode connection, which enhances TFT stability and reduces the overlap area between vias, thereby minimizing alignment issues and maintaining display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protection layer is disposed on the channel layer of metal oxide semiconductor TFT, then the sensitivity to light, water and oxygen is reduced, but the TFT efficiency still deviates over time and heat treatment causing display quality degradation
Solution Approach 1:
The patent divides the insulating layer into multiple sub-layers (first insulating sub-layer and second insulating sub-layer) with different functions. The first sub-layer provides protection while the second sub-layer optimizes electrical characteristics, allowing each layer to be independently optimized for its specific function rather than requiring a single layer to perform all functions.
Solution Approach 2:
Different regions of the insulating structure are given different properties through the multi-sub-layer design. The first sub-layer has properties optimized for protection and stability, while the second sub-layer has properties optimized for electrical performance and efficiency consistency, allowing local optimization of characteristics.
2Reliability
If a via is formed by etching over the drain of TFT for pixel electrode connection, then electrical connection is achieved, but alignment issues and overlap area reduce display quality
Solution Approach 1:
The via structure is segmented into multiple opening sections corresponding to the multi-sub-layer insulating structure. Each sub-layer has a corresponding opening (first opening, second opening, etc.) that together form the complete via path, allowing precise control of alignment at each layer rather than requiring perfect alignment of a single large via.
Solution Approach 2:
The via alignment problem is solved by transitioning from a two-dimensional planar alignment to a three-dimensional stepped structure. The multi-level openings provide vertical stacking that compensates for horizontal alignment tolerances, effectively adding a vertical dimension to solve the alignment issue.
3Reliability
If polycrystalline TFT is used to achieve high carrier mobility, then carrier mobility reaches about 100 cm2/Vs, but it requires manufacturing temperature over 450°C limiting substrate choices
Solution Approach 1:
The patent changes the material parameter of the channel layer from conventional materials to metal oxide semiconductor (such as IGZO), which fundamentally alters the temperature-mobility relationship. This material parameter change enables achieving acceptable carrier mobility at significantly lower manufacturing temperatures compared to polycrystalline TFT.
4Temperature
If amorphous TFT is used to achieve low manufacturing temperature of about 300°C, then substrate flexibility is improved, but carrier mobility only reaches about 1 cm2/Vs insufficient for high fineness applications
Solution Approach 1:
The patent changes the material parameter from amorphous semiconductor to metal oxide semiconductor, which fundamentally improves the carrier mobility parameter while maintaining the low-temperature processing advantage. This material parameter change bridges the gap between amorphous and polycrystalline TFT performance.
Data Source
AI summary
A display panel includes a TFT substrate, an opposite substrate and a display layer. A TFT of the TFT substrate has a drain. A first insulating layer has a first sub-layer and a second sub-layer disposed on the drain sequentially. The first sub-layer has a first opening with a first width. The second sub-layer has a second opening with a second width on the first opening. The first and second openings form a first via, and the second width is greater than the first width. A passivation layer is disposed on the first insulating layer. A second insulating layer is disposed on the passivation layer. A pixel electrode layer is disposed on the second insulating layer and disposed in the first via to connect the drain. The display layer is disposed between the TFT substrate and the opposite substrate.