Stepped Multilayer Wiring Structure for Leakage Current Suppression
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Solution Overview
Problem
The rapid miniaturization of semiconductor integrated circuit devices poses challenges in minimizing capacitance loss and preventing time-dependent dielectric breakdown, particularly due to increasing leakage currents in multilayer wiring structures, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor integrated circuit device design featuring a substrate with a front-end-of-line (FEOL) and back-end-of-line (BEOL) structure, where the BEOL structure includes a carbon-containing insulating film with varying carbon content and a stepped wiring layer configuration, minimizing capacitance loss and signal interference through a self-alignment method without additional processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If line width and pitch of multilayer wiring structures are decreased to enable device miniaturization, then device functionality and integration are improved, but leakage current increases and capacitance loss worsens
Solution Approach 1:
The patent applies local quality by creating a stepped wiring layer structure where different portions of the wiring layer have different heights. Specifically, a first portion of the wiring layer is formed at a first height and a second portion is formed at a second height different from the first height. This local structural variation reduces the overlapping area between adjacent wiring layers, thereby minimizing capacitance loss and signal interference while maintaining high device integration.
2Productivity
If line width and pitch of multilayer wiring structures are decreased to enable device miniaturization, then device functionality and integration are improved, but leakage current increases causing time-dependent dielectric breakdown
Solution Approach 1:
The stepped wiring layer structure with varying heights reduces the electric field concentration and leakage current paths between adjacent layers. By having portions at different heights, the dielectric breakdown risk is reduced while maintaining miniaturization benefits.
Solution Approach 2:
The patent introduces vertical dimensionality variation by forming wiring layers at different heights (first height and second height). This three-dimensional arrangement reduces the two-dimensional crowding and associated leakage current issues, improving reliability while enabling further miniaturization.
3Ease of manufacture
If traditional planar wiring layer structure is used, then manufacturing process is simple, but capacitance loss and signal interference between adjacent wiring layers increase
Solution Approach 1:
The patent modifies the traditional planar structure by creating local height variations in the wiring layer. A first portion is formed at a first height and a second portion at a second height, reducing capacitance loss while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces capacitance loss and signal interference, enhancing the electrical characteristics and reliability of semiconductor integrated circuit devices by optimizing the carbon content and structure of insulating films and wiring layers, thereby preventing time-dependent dielectric breakdown.
Implementation Method 1
a carbon-containing insulating film with varying carbon content
Data Source
AI summary
A semiconductor integrated circuit device includes a substrate; a transistor on the substrate; an interlayer insulating film on the transistor; an insulating liner on the interlayer insulating film; a first insulating film on the insulating liner; and a first wiring layer on the interlayer insulating film and surrounded by the insulating liner. A height of a top surface of the first insulating film in a vertical direction from a main surface of the interlayer insulating film is different than a height of a top surface of the first wiring layer in the vertical direction. A step exists between the top surfaces of the first wiring layer and the first insulating film. A height of the first insulating film is greater than a height of the first wiring layer. A width of the first wiring layer gradually narrows as the first wiring layer extends upwards along the vertical direction.