Stepped Wiring Portions for 3D Semiconductor Memory Contact Area Reduction

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Solution Overview

Problem

In three-dimensional semiconductor memory devices, the increased number of laminated layers and conducting layers leads to a larger contact area, which complicates the extraction of conducting layers to external circuits, resulting in a larger occupation area and potential downsizing issues.

Innovation Solution

The implementation of stepped wiring portions with alternating contact formation areas on conducting layers, where some layers have exposed contact formation areas and others are covered, reduces the number of steps and occupation area, allowing for more efficient connection to external circuits while maintaining the three-dimensional memory cell array structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of laminated layers and conducting layers is increased to increase memory capacity, then the storage capacity is improved, but the contact area (stepped portion) area increases, leading to larger occupation area and downsizing issues

Engineering Contradiction:

Improvememory capacityVSAvoidcontact area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent divides the contact formation into multiple discrete contact holes at different heights in the stepped wiring portion, rather than forming a single large contact area. Each contact hole connects to specific conducting layers at different levels, segmenting the overall contact function into distributed, height-specific contact points that reduce total contact area while maintaining connectivity to all necessary conducting layers

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent utilizes the vertical dimension (height) to differentiate contact formation, creating contact holes at multiple height levels within the stepped wiring portion. This vertical stratification allows contacts to be formed at different elevations corresponding to different conducting layers, transforming a two-dimensional contact area problem into a three-dimensional solution that reduces footprint area while maintaining all necessary electrical connections

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the number of laminated layers and conducting layers is increased to increase memory capacity, then the storage capacity is improved, but the occupation area increases, resulting in downsizing issues

Engineering Contradiction:

Improvememory capacityVSAvoidoccupation area

Core Design Contradiction:

Quantity of substanceVSVolume of moving object

Solution Approach 1:

The stepped wiring portion is segmented into multiple height levels with discrete contact holes at each level, allowing the occupation area to be distributed vertically rather than expanded horizontally. This segmentation enables high-density interconnection without proportionally increasing the planar footprint

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a nested structure where contact holes are positioned within the stepped wiring portion at different heights, with each contact hole nested at a specific elevation level. This nesting approach allows multiple contact connections to be contained within a compact vertical space, reducing the overall occupation area while maintaining connectivity to all conducting layers

Inventive Principle:

Principle #7Nested doll (Nesting)

3Adaptability or versatility

If the contact area is increased to connect more conducting layers, then the connection completeness is improved, but the device complexity increases

Engineering Contradiction:

Improveconnection completenessVSAvoidstepped wiring structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by forming contact holes with specific properties at specific height levels within the stepped wiring portion. Each contact hole is positioned and sized according to the local requirements of the conducting layers it connects to, rather than using a uniform contact structure throughout. This localized optimization maintains connection completeness while managing device complexity through targeted, height-specific contact formation

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10186520B2Semiconductor memory devices including a memory cell array and stepped wiring portions, and manufacturing methods thereof

Publication Date: 2019.01.22 KIOXIA CORP

AI summary

A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner. The first conducting layers are connected to the memory cells and are arrayed in a laminating direction. Stepped wiring portion includes a plurality of second conducting layers. The plurality of second conducting layers connect the first conducting layers and external circuits. At least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the first side portion side. Other ones of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the second side portion side.