Stepwise Capacitor Structure for Inductance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional hierarchical capacitor structures face inefficiencies due to high inductance, which affects noise processing and current delivery, especially in electronic circuits where conductive vias do not effectively connect in parallel, leading to reduced capacitance and increased inductance, impacting noise suppression across different frequency ranges.
Innovation Solution
A stepwise capacitor structure with a multi-tier design, featuring conductive layers and dielectric layers that allow for minimum impedance current paths, enabling effective parallel connections and adjustable capacitance to optimize noise suppression across high, medium, and low-frequency ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional hierarchical capacitor structures are used, then capacitance is provided for noise suppression, but inductance increases due to ineffective parallel connections of conductive vias
Solution Approach 1:
The capacitor structure is divided into multiple tiers with conductive layers at different heights, creating multiple parallel current paths that segment the overall inductance into smaller components, thereby reducing total inductance while maintaining capacitance
Solution Approach 2:
The invention transitions from a conventional planar capacitor structure to a three-dimensional multi-tier structure, utilizing vertical stacking to create additional current paths and reduce the effective inductance area, thus solving the inductance problem while preserving noise suppression functionality
2Reliability
If die side capacitors are disposed on the same surface with the IC, then noise processing ability is improved, but inductance increases due to spacing requirements from chip packaging
Solution Approach 1:
The capacitor structure is nested within the chip packaging structure itself, with conductive layers integrated into the substrate, allowing the capacitor to be positioned as close as possible to the die load without being constrained by external packaging spacing requirements, thereby minimizing inductance while maintaining noise processing capability
3Quantity of substance
If multiple conductive vias are used to connect capacitor structures, then capacitance is enhanced, but inductance increases due to via length and ineffective parallel connection
Solution Approach 1:
Multiple conductive layers are merged and connected through conductive vias to form parallel current paths, where the combined effect of multiple short via connections reduces total inductance while the increased conductive surface area enhances capacitance, simultaneously achieving both goals
Data Source
AI summary
A stepwise capacitor structure includes at least one stepwise conductive layer. The stepwise capacitor represents a feature of multiple capacitors. When currents flow through the stepwise capacitor, different current paths are presented in between an upper conductor and a bottom conductor of the stepwise capacitor in response to different current frequency; different inductor is induced in each path and decoupled by a stepwise capacitor structure as disclosed herein.