3D Memory Strings with Stepwise Conductive Layers
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Solution Overview
Problem
Current semiconductor storage devices face challenges in cost-effective refinement due to the limitations of photolithography technology and the high cost of EUV exposure devices, and the manufacturing process of three-dimensional memory strings is complex and costly.
Innovation Solution
A non-volatile semiconductor storage device with a configuration of memory strings comprising columnar semiconductor layers, charge trap layers, and conductive layers, where the conductive layers are formed in a stepwise manner and covered with a protection insulation layer, allowing for efficient integration and reduced manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography technology is used for refinement, then manufacturing cost is reduced, but resolution limit is reached around 40 nm design rule
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple conductive layers and insulation layers in the vertical direction. This allows continued scaling and refinement beyond the 40 nm photolithography resolution limit by utilizing the third dimension (height) rather than solely reducing lateral dimensions.
2Manufacturing precision
If EUV exposure devices are introduced for further refinement, then resolution limit is exceeded, but manufacturing cost increases significantly
Solution Approach 1:
Instead of investing in expensive EUV exposure equipment to achieve sub-40 nm lateral resolution, the patent achieves further refinement by stacking multiple layers vertically. This approach maintains compatibility with existing ArF immersion lithography equipment while achieving higher integration through three-dimensional memory string structures.
3Quantity of substance
If three-dimensional memory strings are implemented, then integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple manufacturing operations into unified processes. For example, multiple conductive layers and insulation layers are laminated and patterned together in integrated steps, and the memory string structure combines charge trap layers, columnar semiconductors, and multiple gates into a single vertical architecture, reducing the number of separate manufacturing processes required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high integration and cost-effective manufacturing of semiconductor storage devices with improved integration density and reduced production complexity, while maintaining efficient device operation.
Implementation Method 1
a charge trap layer formed to sandwich an insulation layer with the first columnar semiconductor layer and accumulating charges
Implementation Method 2
the plurality of first conductive layers and the plurality of second conductive layers being covered with a protection insulation layer
Data Source
AI summary
Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction. Respective ends of the plurality of first conductive layers in the first direction are formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers are formed in an area immediately above the top layer of the first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers are covered with a protection insulation layer that is formed continuously with the plurality of first conductive layers and the second conductive layers.