Stepwise Place-Route IC Design Balancing Timing
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Solution Overview
Problem
Traditional place-and-route (P&R) processes for integrated circuits and field-programmable gate arrays are inefficient, as they involve sequential and separate steps of placement and routing, leading to inaccurate initial placement, constrained routing, and lengthy processing times, which can result in unbalanced timing distribution and delayed feedback on operating frequency.
Innovation Solution
The stepwise place-route (SPR) approach combines placement and routing in an interleaved sequence, using accurate timing information from previous steps to refine subsequent decisions, allowing for incremental and accurate resource management and providing immediate feedback on achievable frequencies by prioritizing critical sub-parts of the design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential place-and-route (P&R) process is used, then placement and routing can be completed, but processing time is lengthy and timing distribution is unbalanced
Solution Approach 1:
The patent divides the netlist into multiple subsets of cells and processes them in sequential steps rather than all at once. Each step places and routes a subset of cells, allowing incremental completion and early feedback on timing characteristics without waiting for the entire design to be processed.
Solution Approach 2:
The patent performs placement and routing on critical subsets of cells before finalizing the entire design. By prioritizing certain cell subsets based on timing criticality, the method establishes timing benchmarks early and uses them to guide subsequent placement decisions for remaining cells.
2Manufacturing precision
If traditional separate placement then routing approach is used, then routing can be performed, but placement accuracy is insufficient leading to constrained routing
Solution Approach 1:
The patent calculates timing characteristics after each placement and routing step on cell subsets. This timing information is fed back to influence subsequent placement decisions, allowing the system to learn from previous steps and improve placement accuracy iteratively while maintaining routing flexibility.
Solution Approach 2:
The patent makes the placement process dynamic by adjusting placement strategies based on timing feedback from previously processed cell subsets. The system adapts placement decisions in real-time during the incremental process rather than committing to fixed placement early on.
3Measurement precision
If complete P&R run is performed, then full timing analysis can be done, but designer feedback time is delayed
Solution Approach 1:
The patent performs partial placement and routing on selected subsets of cells rather than completing the entire design first. This partial action provides sufficient timing information for early feedback while avoiding the full processing time of a complete P&R run, allowing designers to iterate on critical paths first.
Data Source
AI summary
A technology is described for generating placement and routing for a netlist of an integrated circuit (IC) design. The netlist for the IC design is partitioned into multiple subsets of cells. The subsets of cells are prioritized. Multiple stepwise place and route iterations are performed for the multiple subsets of cells. A first subset of cells with a first priority is placed in an arrangement representing the IC design. Wire connections are routed between the cells of the first subset of cells. A second subset of cells is placed relative to one another and the first subset of cells in the arrangement. Wire connections are routed between the cells of the second subset of cells and the cells of the first subset of cells.