Memory Device Programming with Stepwise Program-Allow Voltage Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As the bit number of data stored in a memory cell increases, the distance between threshold voltages of memory cells storing different data narrows, leading to reduced reliability in memory devices.

Innovation Solution

A memory device with a control circuit that controls a voltage generator and page buffer group to apply program allow voltages stepwise based on the number of program loops, and uses different program allow voltages for selected and unselected memory cells to manage threshold voltage distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the bit number of data stored in a memory cell increases, then the storage capacity is improved, but the distance between threshold voltages of memory cells storing different data narrows, leading to reduced reliability

Engineering Contradiction:
Improvestorage capacityVSAvoidreliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies dynamics by making the program allow voltage adjustable and variable across different program loops. The voltage level is dynamically changed based on the number of program loops performed, allowing the system to adapt to the narrowing threshold voltage distance in multi-bit memory cells while maintaining reliable programming operations

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter (program allow voltage) as a function of program loop count. By increasing the program allow voltage in subsequent program loops, the system compensates for the reduced threshold voltage separation in high-capacity memory cells, thereby maintaining programming reliability while achieving high storage capacity

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a fixed program allow voltage is applied to all selected bit lines, then the device complexity is reduced, but the threshold voltage distribution cannot be effectively managed, leading to reduced reliability

Engineering Contradiction:
Improvedevice complexityVSAvoidreliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements a dynamic voltage control scheme where the program allow voltage is adjusted based on program loop count. This dynamic approach effectively manages threshold voltage distribution without requiring complex per-cell voltage control, achieving reliability improvement with moderate complexity increase

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the programming process into multiple program loops with different voltage levels. By dividing the programming operation into stages and applying different program allow voltages to different loops, the system effectively manages threshold voltage distribution while maintaining reasonable device complexity

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12431199B2Memory device and operating method of the memory device
Publication Date: 2025.09.30 SK HYNIX INC
  • US12431199B2 patent drawing
  • US12431199B2 patent drawing
  • US12431199B2 patent drawing

AI summary

A memory device, and an operating method of the memory device, includes a plurality of memory cells connected between word lines and bit lines and a voltage generator for generating a program voltage or a pass voltage, which is applied to the word lines. The memory device also includes a page buffer group for applying program allow voltages or a program inhibit voltage to the bit lines and a control circuit for controlling the voltage generator and the page buffer group in response to a command. In a program operation of selected memory cells connected to a selected word line among the word lines, the control circuit controls the page buffer group such that the program allow voltages are increased stepwise according to a number of program loops performed on the selected memory cells.