Stepwise Internal Spacers for Stacked Nanoribbon Transistors
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in achieving uniform etching for internal spacer structures in stacked nanoribbon semiconductor devices, which often results in uneven spacing and potential electrical shorting between gate and source or drain regions due to the vertical stacking of transistors.
Innovation Solution
A stepwise fabrication process is employed, where each stacked transistor is processed separately to maintain uniform etching rates, involving the formation of protective liners and selective lateral spacer etches around exposed nanoribbons, ensuring uniformity and preventing shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If internal spacer structures are formed in stacked nanoribbon semiconductor devices, then parasitic capacitance is reduced and electrical shorting is prevented, but non-trivial fabrication challenges arise due to the complexity of the stacked structure
Solution Approach 1:
The fabrication process is segmented into separate processing steps for each stacked transistor. Each nanoribbon stack is processed independently through selective etching operations, allowing the formation of internal spacers in a stepwise manner rather than attempting to process the entire stacked structure simultaneously. This segmentation reduces fabrication complexity while maintaining electrical isolation.
Solution Approach 2:
Protective liners are formed on specific nanoribbons before the etching process begins. This preliminary action protects certain regions from etching while allowing internal spacers to be formed in other regions. The selective protection enables precise control over spacer formation locations and prevents electrical shorting during fabrication.
2Manufacturing precision
If uniform etching is applied to stacked nanoribbon structures, then internal spacer structures can be formed, but uneven spacing occurs due to the vertical stacking configuration
Solution Approach 1:
Different etching conditions and protective liner configurations are applied to different regions of the stacked structure. Each nanoribbon stack receives localized processing tailored to its specific geometry and position, ensuring that internal spacers are formed with precise spacing control. This local quality approach allows uniform spacing to be achieved despite the vertical stacking configuration.
Solution Approach 2:
The fabrication process uses dynamic, stepwise etching operations where protective liners are selectively removed and reformed between etching steps. This dynamic approach allows the etching conditions to be adjusted for each individual nanoribbon stack, maintaining etching uniformity while achieving consistent spacing across the stacked structure.
3Shape
If separate processing is applied to each stacked transistor to maintain uniform etching, then spacing uniformity is improved, but fabrication time and process complexity increase
Solution Approach 1:
While separate processing steps are used for each nanoribbon stack, the protective liner formation and etching operations are merged into a coordinated sequence that can be performed in an integrated manner. Multiple nanoribbon stacks are processed through the same series of steps, allowing spacing uniformity to be maintained while reducing overall fabrication time compared to completely independent processing of each stack.
Data Source
AI summary
Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. In an example, an upper (e.g., n-channel) device and a lower (e.g., p-channel) device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where the upper device is located vertically above the lower device. According to some embodiments, an internal spacer structure extends between the nanoribbons of the upper device and the nanoribbons of the lower device along the vertical direction, where the spacer structure has a stepwise or an otherwise outwardly protruding profile as it extends between the nanoribbons of the upper device and the lower device. Accordingly, in one example, a gate structure formed around the nanoribbons of both the n-channel device and the p-channel device exhibits a greater width in the region between the nanoribbons of the n-channel device and the nanoribbons of the p-channel device.