Stereo Vision System Using Multi-Resolution Disparity Processing
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Solution Overview
Problem
Stereo vision systems with modular camera units have limited depth measurement capabilities due to small camera spacing, and systems with wider camera spacing require large memories and increased costs for hardware accelerators to process high-resolution images.
Innovation Solution
A stereo vision system that employs a hardware accelerator with smaller memories and a lower disparity search range, which downsamples high-resolution images, generates a reference disparity map, partitions images into sub-images, and merges disparity maps to produce a disparity map for high-resolution images, reducing overall system cost and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cameras are spaced wider apart to improve depth measurement capabilities, then depth measurement precision is improved, but memory size and hardware accelerator cost increase
Solution Approach 1:
The patent divides the high-resolution image processing task into multiple low-resolution stages. The hardware accelerator first processes downsampled images to generate a coarse disparity map, then processes only relevant sub-regions at full resolution. This segmentation approach allows wide camera baseline processing without requiring large memory capacity to hold all high-resolution image data simultaneously.
Solution Approach 2:
The patent introduces a multi-resolution dimension by processing images at different sampling rates. The coarse-to-fine approach adds a resolution dimension to the processing pipeline, allowing the system to handle wide baseline scenarios with reduced memory requirements by operating primarily in the downsampled domain and only transitioning to full resolution when necessary.
2Measurement precision
If high-resolution images are processed directly to maintain image quality, then measurement precision is improved, but device complexity and processing time increase
Solution Approach 1:
The patent performs preliminary processing on downsampled images to generate a coarse disparity map before processing high-resolution images. This preliminary action identifies regions of interest and establishes initial depth estimates, which guide subsequent high-resolution processing. The hardware accelerator is configured to perform this preliminary low-resolution processing first, reducing the complexity burden on the high-resolution processing stage.
Solution Approach 2:
The patent applies partial processing to high-resolution images by only processing specific sub-regions identified as containing objects of interest, rather than processing the entire high-resolution image. This selective processing approach maintains measurement precision for relevant areas while significantly reducing hardware accelerator complexity and processing time.
3Quantity of substance
If downsampled images are used to reduce memory requirements, then memory size is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent segments the processing into multiple resolution levels. Downsampled images are used for initial disparity estimation and to identify regions of interest, while high-resolution sub-regions are processed separately to refine the disparity map. This multi-level segmentation allows the system to use small memories for the majority of processing while maintaining high precision in the final output through selective high-resolution processing.
Solution Approach 2:
The patent uses the coarse disparity map generated from downsampled images as an intermediary to guide high-resolution processing. This intermediary structure provides initial depth estimates that inform which high-resolution sub-regions need processing and how to interpret the final disparity values, bridging the gap between low-resolution memory efficiency and high-resolution measurement precision.
Data Source
AI summary
A system includes a downsampling circuit, a stereo disparity engine, and a merge circuit. The downsampling circuit is configured to generate a first two-dimensional array by down sampling a second two-dimensional array, and generate a third two-dimensional array by down sampling a fourth two-dimensional array. The stereo disparity engine is configured to generate a first disparity map relating elements of the first two-dimensional array to elements of the third two-dimensional array, generate a second disparity map based on the first disparity map, a first sub-array of the second two-dimensional array and a second sub-array of the fourth two-dimensional array, and generate a third disparity map based on the first disparity map, a third sub-array of the second two-dimensional array and a fourth sub-array of the fourth two-dimensional array. The merge circuit is configured to combine the second disparity map and the third disparity map to generate a fourth disparity map.