Shallow Trench Isolation Air Gaps for NAND Memory Leakage Reduction
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Solution Overview
Problem
Current fabrication techniques for high-density semiconductor devices, such as NAND flash memory, face challenges in reducing parasitic capacitance and word line-active area leakage as feature sizes decrease, affecting storage capacity and reliability.
Innovation Solution
The formation of shallow trench isolation (STI) air gaps within the semiconductor substrate, including methods to create air gaps in the interpoly dielectric (IPD) layer above STI air gaps, helps reduce parasitic capacitance and leakage by using dielectric materials like polysilazane and silicon dioxide, and selectively removing portions of the IPD layer to optimize electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are reduced to increase storage density, then storage capacity increases, but parasitic capacitance and word line-active area leakage increase
Solution Approach 1:
Air gaps are formed by removing dielectric material from specific regions between memory cell strings, extracting the harmful dielectric that causes parasitic capacitance while maintaining the physical structure needed for high-density storage
Solution Approach 2:
The structure transitions from uniform dielectric filling to non-uniform composition with air gaps strategically positioned in inter-string isolation regions, creating local electrical isolation where needed while maintaining dielectric continuity in other areas
2Ease of manufacture
If conventional STI structures are used without air gaps, then manufacturing is simpler, but cell-to-cell crosstalk and parasitic capacitance are higher
Solution Approach 1:
The continuous dielectric material in the STI structure is segmented into discrete regions separated by air gaps, dividing the isolation function into multiple zones that provide both mechanical support and electrical isolation
Solution Approach 2:
Air gaps serve as intermediary regions between adjacent memory cell strings, providing electrical isolation and reducing capacitive coupling while maintaining the physical continuity of the STI structure for mechanical support
Data Source
AI summary
A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a first dielectric material in the trench, forming a second dielectric material above the first dielectric material, forming a first air gap in the first dielectric material in the trench, and forming a second air gap in the second dielectric material above the first air gap.


