STI-Bounded SPAD Pixel Design for CMOS Integration

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Solution Overview

Problem

The existing manufacturing processes for single-photon avalanche diodes (SPADs) are costly and incompatible with commercial CMOS technologies, leading to large pixel sizes, high dark current rates, and low spatial resolution, making it difficult to produce compact and high-performance sensor arrays.

Innovation Solution

The use of trench isolation guard rings and shallow trench isolation (STI) processes in CMOS technologies to planarize and isolate p-n junctions, allowing for the creation of compact SPADs with improved fill factors and reduced dark current rates, enabling the integration of signal processing circuitry and miniaturization of SPADs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional manufacturing processes are used for SPADs, then device performance can be achieved, but pixel size becomes large and manufacturing cost increases

Engineering Contradiction:

Improvepixel sizeVSAvoidmanufacturing cost

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent changes the manufacturing process parameters by adopting CMOS-compatible fabrication techniques, including shallow trench isolation (STI) and standard doping processes, to reduce pixel size while maintaining compatibility with commercial manufacturing workflows

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent makes the SPAD manufacturing process universal by using standard CMOS fabrication processes that can be integrated with existing semiconductor manufacturing infrastructure, enabling mass production without requiring specialized equipment or processes

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Manufacturing precision

If pixel area is reduced for compact SPADs, then spatial resolution improves, but dark current rate increases

Engineering Contradiction:

Improvespatial resolutionVSAvoiddark current rate

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and removes the isolation structures from previous designs, using only shallow trench isolation without deep isolation trenches or guard rings, thereby eliminating sources of dark current while maintaining small pixel dimensions for high spatial resolution

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the isolation depth parameter from deep trenches to shallow trenches only, reducing the isolation structure depth to minimal necessary levels, which decreases capacitance and dark current generation while preserving pixel compactness

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If fill factor is increased for better photon detection, then detection efficiency improves, but pixel area increases

Engineering Contradiction:

Improvedetection efficiencyVSAvoidpixel area

Core Design Contradiction:

Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent removes unnecessary isolation structures and guard rings that previously occupied significant pixel area, thereby increasing the fill factor and light-sensitive area without increasing the overall pixel footprint, improving detection efficiency in compact pixels

Inventive Principle:

Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in smaller pixel sizes, lower dark current rates, and improved spatial resolution, facilitating the production of high-performance SPAD arrays with reduced power consumption and increased detection efficiency, suitable for various imaging applications.

Implementation Method 1

When a free carrier enters the high-field region of the pn junction in the Geiger mode, the carrier is accelerated by the electric field and the accelerated carrier collides with the lattice to cause impact ionization.

Methodology Applied

Scientific EffectImpact ionization:

Implementation Method 2

Above the breakdown voltage, carriers are generated in the junction faster than they are extracted to cause an avalanche breakdown process.

Methodology Applied

Scientific EffectAvalanche breakdown: Avalanche Breakdown

Implementation Method 3

a trench ring formed in the well region to create a trench from the top substrate surface that surrounds a first portion of the well region and leave a second portion of the well region outside the trench ring, the trench ring filled with an insulator material to form a guard ring to spatially confine the first portion of the well region

Methodology Applied

Scientific EffectPhysical containment: Physical Containment