Buried Power Rail Structure in STI for FinFET Source Connection
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and complexity in chip layout due to decreased routing area, particularly in embedding power rails in shallow trench isolation (STI) regions, which affects the integration density and efficiency of semiconductor devices.
Innovation Solution
A method for manufacturing a semiconductor structure with power rails embedded in the STI region, where the power rails are formed in the front end of line (FEOL) process, extending in a specific direction and electrically connected to doping regions and the substrate, allowing for efficient power supply distribution and reduced layout complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are embedded in STI region between fin rows, then power distribution is achieved, but routing area decreases and layout becomes more complicated
Solution Approach 1:
The patent merges the power rail structure with the STI isolation regions by forming conductive plugs and metal layers that integrate power distribution pathways within the existing STI framework, thereby achieving power distribution without requiring separate dedicated routing areas
Solution Approach 2:
The patent utilizes vertical dimension by forming conductive plugs extending through the STI region and multiple metal layers at different heights, transforming the power distribution from a planar routing problem to a three-dimensional structure that efficiently uses vertical space for power delivery
2Reliability
If power rails are embedded deep in the IC in FEOL, then power distribution network is established, but connection to source and drain areas requires additional local interconnects increasing device complexity
Solution Approach 1:
The patent makes the STI regions serve dual functions: both as isolation structures between active devices and as pathways for power distribution, eliminating the need for separate power routing infrastructure and reducing overall device complexity
Solution Approach 2:
The patent forms the power rail structure including conductive plugs and metal layers during the FEOL process before transistor activation, preparing the power distribution pathways in advance so that subsequent processing steps can proceed without additional complexity
Data Source
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AI summary
A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region (220) on a well region (10_1, 15_1) of a substrate (210), a plurality of transistors, and a power rail (40_1, 40_2). Each of the transistors includes at least one fin (20_1, 20_2, 20_3, 20_4), a gate electrode formed on the fin, and a doping region (25_1, 25_2, 27_1, 27_2) formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.