STI Dishing Suppression via Asymmetric Etching for Planar Resistors
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Solution Overview
Problem
The integration of high resistance polysilicon resistors in IC design faces challenges due to significant STI dishing effects, leading to metal residue issues during metal polishing, which causes shorting and failure of resistors, especially when STI dimensions are large, such as 10×10 μm2, making it difficult to remove metal residue between Hi-R resistors.
Innovation Solution
The method involves forming shallow trench isolation (STI) features with varying widths, where the second STI features with a narrower width are made more vulnerable to etching processes, reducing their thickness difference with wider STI features, and using ion implantation and etching processes to compensate for height differences without adding complex steps, ensuring a planarized surface for resistor formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If large STI dimensions are used to accommodate Hi-R resistors, then the resistors can be formed on the STI structure, but significant STI dishing effect occurs causing the STI surface to be non-planar
Solution Approach 1:
The patent applies different etching rates to different STI regions by selectively exposing them during the etching process. Wider STI features (first STI features) are exposed and etched at a first rate, while narrower STI features (second STI features) are covered by a mask and etched at a second rate, creating localized quality differences that compensate for dishing effects and achieve surface planarity.
2Device complexity
If conventional STI structures are used, then the fabrication process is simple, but metal residue accumulates during polishing causing shorting and resistor failure
Solution Approach 1:
The patent performs preliminary planarization by selectively etching the STI structure before forming the metal interconnect layers. This preliminary action removes the dishing effect and creates a planar surface, preventing metal residue accumulation during subsequent polishing operations and ensuring reliable resistor operation.
Solution Approach 2:
The patent applies a mask layer selectively to certain STI regions before etching to prevent over-etching and dishing. This preliminary protective action counteracts the harmful dishing effect that would otherwise lead to metal residue and reliability issues.
3Ease of manufacture
If uniform STI width is used throughout the structure, then the fabrication process is straightforward, but height differences between STI features cannot be compensated
Solution Approach 1:
The patent intentionally creates asymmetric STI structures with different widths (first STI features with wider width, second STI features with narrower width) and applies asymmetric masking and etching processes. This asymmetry enables differential etching rates that compensate for height differences and achieve uniform top surfaces across diverse STI features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the height difference between STI features, preventing metal residue accumulation and shorting issues, ensuring the integrity of high resistance resistors on large dimension STI structures.
Implementation Method 1
performing an ion implantation process to the substrate using the implantation mask
Implementation Method 2
performing an etching process to the substrate... performing an etching process to the dielectric material layer, reducing a thickness of the second STI feature
Data Source
AI summary
An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate. The first width is less than the second width. The first STI feature has an etch-resistance less than that of the second STI feature.