STI Etching Depth Uniformity via Quadrant Rotation

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Solution Overview

Problem

The existing STI etching process for CIS products results in HDP filling defects due to depth discrepancies in STI areas, leading to edge voids, which are not adequately addressed by current control methods as production increases and machine maintenance demands intensify.

Innovation Solution

A method involving the division of a wafer into quadrants and sequential STI etching with angle matching and rotation to ensure uniform depth formation in both pixel and logical areas, followed by photoresist application and further etching to prevent voids during HDP filling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If two-step STI etching is performed with different depths for pixel and logical areas, then the etching process meets process requirements for CIS products, but HDP filling defects occur due to depth discrepancies causing edge voids

Engineering Contradiction:
ImproveSTI depth uniformityVSAvoidHDP filling quality
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The wafer surface is divided into four quadrants, and the etching process is segmented into multiple passes with different quadrant orientations. Each pass etches a portion of the wafer while avoiding the cantilever shadow effect on critical areas, thereby achieving uniform STI depth across the entire wafer surface and preventing HDP filling defects

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The wafer orientation is dynamically changed between etching passes by rotating it to present different quadrants to the cantilever. This dynamic repositioning ensures that no single area is consistently affected by the cantilever shadow, achieving uniform etching depth across all regions and eliminating edge voids during HDP filling

Inventive Principle:
Principle #15Dynamics

2Reliability

If STI and HDP are processed at selected machines with better process capability, then void defects are reduced, but the control method cannot meet product delivery demands with increased production volume and machine maintenance requirements

Engineering Contradiction:
Improvevoid defect reductionVSAvoidproduct delivery capacity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The etching parameters are changed by modifying the wafer orientation and etching sequence rather than relying on specific machine capabilities. This parameter change allows any standard etching machine to achieve uniform STI depth and prevent voids, thereby scaling production without being constrained by machine selection and maintenance bottlenecks

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves in-plane depth uniformity during the STI etching process, effectively preventing voids from forming during HDP filling, thus enhancing the reliability of the HDP filling process.

Implementation Method 1

placing the wafer on an electrostatic chuck of an etching chamber

Methodology Applied
Scientific EffectElectrostatic attraction: Electrostatics

Implementation Method 2

synchronously performing STI etching to the pixel areas and the logical areas

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS11342217B1Method for improving HDP filling defects through STI etching process
Publication Date: 2022.05.24 SHANGHAI HUALI MICROELECTRONICS CORP
  • US11342217B1 patent drawing
  • US11342217B1 patent drawing
  • US11342217B1 patent drawing

AI summary

The present disclosure provides a method for improving HDP filling defects through an STI etching process, comprises a wafer uniformly distributed with pixel areas and logical areas, and dividing the wafer into quadrants 1 to 4; placing the second quadrants in an etching chamber in a manner of facing to a cantilever of an etching machine; etching the wafer to form STI areas with the same depth in the pixel areas and the logical areas of the quadrants 1 to 4; removing the wafer from the etching machine and covering the STI areas of the pixel areas with a photoresist; placing the wafer on an electrostatic chuck of the etching chamber again, and enabling any quadrant except the second quadrant to face to the cantilever; continuously etching the STI areas of the logical areas of the quadrants 1 to 4 to form deep STI areas.