STI Gate Structure Layout to Prevent High-Aspect-Ratio Flop Over
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Solution Overview
Problem
The high aspect ratio of gate structures on shallow trench isolation regions in semiconductor technology leads to gate structure flop over after gate etching, causing significant defectivity issues in downstream integration.
Innovation Solution
A semiconductor structure with a lowered gate aspect ratio on the shallow trench isolation region is implemented, achieved by using a first trench dielectric material with a higher height than a second trench dielectric material in the active device region, thereby reducing the gate structure's aspect ratio and preventing flop over.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate structures are formed on shallow trench isolation regions with high aspect ratio, then device scaling is achieved, but gate structure flop over occurs causing defectivity issues
Solution Approach 1:
The patent applies local quality by creating different trench dielectric material heights in different regions: a first height in the shallow trench isolation region and a second height in the active device region. This localized differentiation allows the gate structure to have reduced aspect ratio and prevent flop over in the STI region while maintaining proper device function in the active region.
Solution Approach 2:
The patent changes the physical parameter of trench dielectric material height to resolve the contradiction. By adjusting the height parameter of the trench dielectric material in the STI region relative to the active device region, the gate aspect ratio is modified, preventing flop over while maintaining scaling benefits.
2Reliability
If trench dielectric material height is increased in shallow trench isolation region, then gate aspect ratio is reduced preventing flop over, but device structure complexity increases
Solution Approach 1:
The patent implements local quality by differentiating the trench dielectric material height between the STI region and active device region. This localized structural modification targets only the specific area where gate flop over occurs, rather than changing the entire device structure, thus minimizing overall complexity while solving the stability issue.
Data Source
AI summary
A semiconductor structure is provided that has a lowered gate aspect ratio on the shallow trench isolation area to prevent gate structure flop over. The structure includes a shallow trench isolation region including a first trench dielectric material having a first height. The structure further includes an active device region located adjacent to the shallow trench isolation region. The active device region includes a second trench dielectric material having a second height which is less than the first height.