STI Gate Strap Layout to Reduce Upper-Layer Contact Congestion
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Solution Overview
Problem
The proximity of gate contacts to adjacent metal contacts in semiconductor devices increases the risk of electrical shorting, particularly in non-planar transistor architectures like FinFETs and nanosheet FETs, due to the need for wider gate contacts to connect multiple gates, leading to congestion in upper layers.
Innovation Solution
The gate strap is formed under the gates in the shallow trench isolation region, reducing the width of the gate contact on top of the gates and minimizing the likelihood of electrical shorting by maintaining a safer distance from adjacent metal contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate contacts are made wider to connect multiple gates, then electrical connection reliability between gates is improved, but the risk of electrical shorting with adjacent metal contacts increases
Solution Approach 1:
The gate strap is repositioned from the upper layer to the lower layer (in the shallow trench isolation region), changing the vertical dimension of the connection path. This dimensional relocation allows the gate strap to maintain adequate horizontal spacing from adjacent metal contacts while still providing reliable electrical connection between multiple gates, thereby resolving the contradiction between connection reliability and shorting risk.
2Reliability
If gate contacts are made wider to connect multiple gates, then electrical connection reliability between gates is improved, but congestion in upper layers increases
Solution Approach 1:
The gate strap connection is moved to the lower layer within the shallow trench isolation region, effectively utilizing the vertical dimension to redistribute routing complexity. This relocation reduces congestion in the upper metal layers by transferring the gate-to-gate connection function to a lower plane, thereby maintaining connection reliability while simplifying upper layer routing.
Solution Approach 2:
The gate strap function is extracted from the upper metal layers and placed into the shallow trench isolation region. This extraction removes the source of congestion from the upper layers, allowing for cleaner routing and reduced device complexity in the critical upper interconnect regions while preserving the essential gate connection functionality.
3Ease of manufacture
If gate contacts are made narrower to reduce congestion, then ease of manufacture is improved, but electrical connection reliability between gates deteriorates
Solution Approach 1:
By relocating the gate strap to the lower layer in the shallow trench isolation region, the connection can be formed with narrower dimensions that are easier to manufacture, while the vertical positioning ensures adequate spacing from other structures. This dimensional relocation maintains manufacturing ease while preserving connection reliability through proper spatial arrangement.
Data Source
AI summary
In an attempt to reduce congestion in the upper layers and improve efficiency in semiconductor devices, embodiments comprise a semiconductor device that comprises a substrate, a shallow trench isolation (STI) layer formed on the substrate. The semiconductor device also includes comprises a first gate, a second gate, and a gate strap connecting the first gate to the second gate. The gate strap is formed in the STI layer.