STI Height Control for DRAM Peripheral Circuit Planarity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor device manufacturing processes face challenges with STI protrusion differences between DRAM memory cell and peripheral circuit areas, leading to dishing issues, reduced integration density, and difficulties in forming transistors with varying threshold voltages, which affect the yield and photolithography margin.
Innovation Solution
A method is introduced to form semiconductor devices with STI isolation regions of varying heights by selectively etching the STI in different areas, using a mask to control the etching process, thereby reducing residue and improving the photolithography margin by creating a more uniform surface for patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If STI isolation regions are formed with uniform height across the wafer, then manufacturing simplicity is maintained, but dishing occurs in low density areas during CMP and STI protrusion differences arise between DRAM memory cell and peripheral circuit areas
Solution Approach 1:
The patent applies local quality by forming STI isolation regions with different heights in different areas of the semiconductor device. Specifically, the peripheral circuit area has a first STI height while the memory cell area has a second STI height. This resolves the contradiction by allowing each area to have the optimal STI height for its specific requirements, preventing dishing in low density areas while maintaining proper isolation in high density areas.
2Manufacturing precision
If selective etching of STI is performed to reduce protrusion differences between areas, then photolithography margin is improved, but process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into distinct areas (peripheral circuit area and memory cell area) with different STI heights. This is achieved through selective etching processes that target specific areas. The segmentation allows each area to have optimized photolithography margins according to its pattern density requirements, resolving the contradiction between improved precision and increased process complexity.
3Shape
If CMP is used to planarize the wafer surface after STI formation, then surface uniformity is improved, but dishing occurs in low density areas
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through area-specific STI height control. After CMP planarization, selective etching is performed to create different STI heights in different areas. This ensures that low density areas (peripheral circuits) maintain higher STI protrusion to prevent dishing, while high density areas (memory cells) have lower STI protrusion, thereby maintaining both surface planarity and STI protrusion uniformity across different regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield by reducing residue and dishing issues, allowing for a larger photolithography margin and improved integration density by ensuring uniform STI heights across the semiconductor device, thus addressing the challenges of varying threshold voltages and protrusion differences.
Implementation Method 1
A silicon substrate surface is thermally oxidized to form a buffer silicon oxide film
Implementation Method 2
the silicon nitride film and silicon oxide film are etched
Implementation Method 3
the silicon substrate is etched to form an isolation trench
Implementation Method 4
After the surface of the isolation trench is thermally oxidized
Implementation Method 5
the isolation trench is filled with a silicon oxide film by high density plasma (HDP) CVD
Implementation Method 6
The silicon oxide film on the silicon nitride film is removed by chemical mechanical polishing (CMP)
Implementation Method 7
The exposed silicon nitride film is etched and removed with hot phosphoric acid
Implementation Method 8
the buffer silicon oxide film is etched and removed with dilute hydrofluoric acid to expose the surfaces of active regions
Implementation Method 9
the active region surface is thermally oxidized to form an ion implantation sacrificial silicon oxide film
Implementation Method 10
ion implantation is performed for well formation, channel stop formation and threshold voltage adjustment suitable for respective transistors
Implementation Method 11
the sacrificial silicon oxide film is etched and removed
Implementation Method 12
The active region surface is again thermally oxidized to form a gate silicon oxide film
Implementation Method 13
some gate silicon oxide films are etched and removed, and new gate silicon oxide films are formed
Implementation Method 14
A gate electrode layer of polysilicon or the like is deposited on the gate silicon oxide films and patterned by etching using a resist mask
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.