Semiconductor Isolation Lamination for Flat STI Epitaxy
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Solution Overview
Problem
The pre-cleaning process for epitaxial growth of SiGe layers in semiconductor devices can lead to lattice defects and charge leakage due to dishing of the shallow trench isolation structure, resulting in degraded device performance and yield.
Innovation Solution
A manufacturing method that includes forming a substrate with a multi-layer isolating lamination structure in the trench, forming an epitaxial layer on the active region, and etching off the barrier layer and part of the isolating lamination layer to maintain consistent top surface heights, preventing turf defects and charge leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pre-cleaning process is performed to remove oxide layer on substrate surface, then epitaxial growth quality is improved, but shallow trench isolation structure suffers dishing and lattice defects
Solution Approach 1:
The isolation lamination layer is divided into multiple segments (first isolation layer, second isolation layer, third isolation layer) with different etching resistances. This segmentation allows selective removal of portions during etching processes, enabling the top surface to maintain consistent height while preventing dishing defects in the isolation structure.
Solution Approach 2:
Different portions of the isolation lamination layer are given different etching resistances through material composition variations. The first, second, and third isolation layers have progressively different etching resistances, allowing localized removal of material to achieve a flat top surface while preserving the underlying isolation structure integrity.
2Manufacturing precision
If pre-cleaning process is performed to improve epitaxial growth, then substrate surface cleanliness is improved, but charge leakage occurs due to dishing and fault layers
Solution Approach 1:
The multi-layer isolation structure is segmented into layers with different etching resistances, allowing selective removal of material during etching. This prevents the formation of deep dishing regions that would create fault layers and cause charge leakage, while still enabling adequate cleaning of the substrate surface for epitaxial growth.
Solution Approach 2:
The etching process that could potentially cause dishing is converted into a beneficial tool by using the differential etching resistance of the multi-layer isolation structure. The etching selectively removes material to create a flat top surface, transforming a potential harm (dishing) into a benefit (flat surface that prevents charge leakage).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures a flat top surface of the isolating lamination layer, preventing charge leakage and improving the performance and yield of semiconductor devices by maintaining the integrity of the epitaxial layer and reducing defects.
Implementation Method 1
forming an epitaxial layer covering a top surface of the first active region
Implementation Method 2
etching off the barrier layer and part of the isolating lamination layer in the first region
Data Source
AI summary
The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate, where the substrate includes a first region and a second region, the first region includes a plurality of independent first active regions, adjacent two of the first active regions are isolated by a first trench, and an isolating lamination layer is formed in the first trench; forming a barrier layer covering a top surface of the second region; forming an epitaxial layer covering a top surface of the first active region; and etching off the barrier layer and part of the isolating lamination layer in the first region, where joints of top surfaces of layers in the isolating lamination layer retained in the first region are basically consistent in height.