Semiconductor Structure for STI-Protected Silicide Etching
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Solution Overview
Problem
Shallow trench isolation (STI) in semiconductor devices is susceptible to noise and leakage issues due to unselective etching during the formation of silicide layers, leading to divots and stress at the STI edges, which affect device performance.
Innovation Solution
A method is employed where a dielectric layer is selectively removed to expose specific areas for silicide formation, using a photoresist mask to protect the STI regions, followed by a high-selectivity etching process to prevent damage to the STI and ensure precise silicide layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If unselective etching is used during silicide layer formation, then the etching process is simple and fast, but it causes damage to STI structures including divots and stress at edges
Solution Approach 1:
A mandrel structure is introduced as an intermediary element between the etching process and the STI regions. The mandrel serves as a physical barrier that prevents the etching chemistry from directly contacting and damaging the STI edges, thereby enabling selective protection without requiring complex mask alignment processes
Solution Approach 2:
The mandrel structure is formed in advance before the silicide etching process. This preliminary action establishes protective barriers at the STI edges prior to exposure to etching chemistry, ensuring that the STI structures are pre-protected against potential damage during the subsequent high-selectivity etching process
2Manufacturing precision
If photoresist mask is used to protect STI regions, then STI damage is minimized, but the process complexity increases
Solution Approach 1:
The mandrel structure serves as a simplified intermediary that replaces the need for photoresist masking. By forming the mandrel through direct deposition and patterning on the STI regions, the process eliminates complex photoresist application, alignment, and removal steps while maintaining effective protection of STI edges during etching
Solution Approach 2:
The photoresist masking step is extracted and removed from the process flow. Instead of using photoresist to define protected regions, the mandrel structure is formed directly on the STI regions through deposition and selective removal, thereby simplifying the overall process by eliminating the photoresist handling steps
3Manufacturing precision
If high-selectivity etching is used, then silicide formation precision is improved, but the etching time increases
Solution Approach 1:
The etching process is made selective through local quality differentiation. The mandrel structure creates locally different etching conditions: areas covered by the mandrel are protected while exposed areas undergo etching. This local selectivity enables precise silicide formation only where needed, achieving high manufacturing precision without requiring excessively long etching times across the entire wafer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes damage to STI structures, reduces junction leakage, and enhances device reliability by maintaining electrical isolation and improving flicker noise characteristics.
Implementation Method 1
using a photoresist mask to protect the STI regions
Implementation Method 2
followed by a high-selectivity etching process to prevent damage to the STI
Data Source
AI summary
A method of manufacturing a semiconductor structure is disclosed. The method includes the following operations. An insulation region is formed in a substrate to define an active region in the substrate. A gate structure is formed across the active region. A source or drain region is formed in the active region and adjoins the insulation region. A resist protective dielectric film is formed, wherein the resist protective dielectric film overlaps an interface between the source or drain region and the insulation region, and exposes a portion of the source or drain region and a portion of the gate structure.