STI Protection Structure for Nanostructure FET Etching
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, the challenge of protecting shallow trench isolation (STI) regions during the selective etching process for forming nanostructures in field-effect transistors becomes critical, as existing methods can lead to loss of STI regions and increased parasitic capacitance, affecting device performance and production yield.
Innovation Solution
A shallow trench isolation (STI) protection structure is formed using a liner layer and a hard mask layer with a non-uniform thickness, which is created through a plasma-enhanced chemical vapor deposition (PECVD) process to protect STI regions during the etching of a disposable oxide interposer, ensuring the STI regions are preserved and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If selective etching process is used to form nanostructures, then device integration density is improved, but STI regions are lost and parasitic capacitance increases
Solution Approach 1:
A protection structure comprising a first dielectric material and a second dielectric material is introduced as an intermediary between the etching process and the STI regions. This protection structure selectively protects the STI regions during etching of the disposable oxide interposer material, preventing STI loss while allowing the etching process to proceed for nanostructure formation. The structure is subsequently removed after serving its protective function.
Solution Approach 2:
The protection structure is formed preliminarily before the selective etching process to preemptively protect the STI regions. By establishing this protective barrier in advance, the STI regions are shielded from the harmful effects of the etching process that would otherwise cause their loss and increase parasitic capacitance.
2Productivity
If selective etching process is used to form nanostructures, then device integration density is improved, but parasitic capacitance increases
Solution Approach 1:
The protection structure acts as an intermediary that prevents direct interaction between the etching process and the STI regions. By blocking the etchant from reaching the STI regions, the structure prevents the formation of parasitic capacitance that would otherwise result from STI region loss and subsequent proximity effects.
3Reliability
If STI regions are protected during etching, then device performance is improved, but process complexity increases
Solution Approach 1:
The protection structure is segmented into two distinct dielectric material layers with different functions. The first dielectric material provides primary protection, while the second dielectric material provides additional protection and is selectively removed. This segmentation allows for controlled removal of the protection structure after it has served its purpose, reducing the impact on overall process complexity.
Solution Approach 2:
The protection structure is designed as a temporary, disposable element that is removed after serving its protective function. The selective removal of the second dielectric material allows for recovery of the underlying structures while discarding the protection structure that has completed its protective mission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The STI protection structure effectively prevents loss of STI regions during etching, leading to reduced parasitic capacitance and improved device performance, along with enhanced production yield and throughput.
Implementation Method 1
a plasma-enhanced chemical vapor deposition (PECVD) process forms the hard mask layer
Data Source
AI summary
A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, the fin structure including a fin and alternating layers of a first semiconductor material and a second semiconductor material over the fin; forming shallow trench isolation (STI) regions on opposing sides of the fin structure; forming an STI protection structure on upper surfaces of the STI regions; forming a dummy gate structure over the fin structure; forming source/drain openings in the fin structure to expose the first and second semiconductor materials; replacing the first semiconductor material disposed under the dummy gate structure with a sacrificial material; after the replacing, forming source/drain regions in the source/drain openings; after forming the source/drain regions, removing the sacrificial material and replacing the dummy gate structure with a replacement gate structure.