STI Protection Layer for Parasitic Capacitance Control in FinFETs
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Solution Overview
Problem
The reduction in minimum feature sizes in semiconductor devices leads to issues such as undesirable recessing of Shallow Trench Isolation (STI) regions during the removal of sacrificial layers, causing increased effective capacitance and out fringe capacitance.
Innovation Solution
A protection layer, or hard mask, is formed on the STI regions to prevent recessing during the removal of sacrificial layers, using materials with high etching selectivity relative to STI regions and sacrificial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sacrificial layers are removed to enable device formation, then device integration is achieved, but STI regions experience undesirable recessing causing increased parasitic capacitance
Solution Approach 1:
A protection layer is formed on the STI regions before the sacrificial layer removal process. This preliminary protective measure ensures that when the sacrificial layer is subsequently removed, the STI regions are already shielded and will not undergo undesirable recessing, thus preventing increased parasitic capacitance while still allowing device integration to proceed
Solution Approach 2:
The protection layer acts as an intermediary between the etching process and the STI regions. During sacrificial layer removal, this intermediate layer absorbs the etching impact and prevents direct interaction between the etchant and STI regions, thereby maintaining STI region integrity and preventing parasitic capacitance increase
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated, but STI region recessing becomes more pronounced increasing capacitance
Solution Approach 1:
The protection layer is deposited on STI regions before any etching or removal processes occur. This advance protection is critical when working with reduced minimum feature sizes, as it pre-shields the STI regions from dimensional changes that would otherwise be magnified at smaller scales, maintaining manufacturing precision while enabling higher integration density
Solution Approach 2:
By introducing the protection layer, the physical and chemical parameters of the STI region surface are changed. The protection layer provides different etching resistance and mechanical properties compared to the original STI region, allowing the system to maintain dimensional control precision even as minimum feature sizes are reduced for higher integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the undesirable increase in parasitic capacitance between conductive features by protecting STI regions, maintaining structural integrity and reducing capacitance.
Implementation Method 1
using materials with high etching selectivity relative to STI regions and sacrificial layers
Data Source
AI summary
A method includes forming a shallow trench isolation region aside of a protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. The method further includes forming a hard mask on the shallow trench isolation region, forming a dummy gate stack over the protruding fin, removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure, forming a disposable interposer in the space, removing the dummy gate stack, removing the disposable interposer using an etching chemical, wherein when the disposable interposer is removed, the hard mask is exposed to the etching chemical, and forming a gate stack, wherein a portion of the gate stack is filled in the space.