STI Protection Layer Implantation to Prevent Isolation Recess
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Solution Overview
Problem
The reduction in minimum feature sizes in semiconductor devices leads to issues such as undesirable recessing of Shallow Trench Isolation (STI) regions during the removal of sacrificial layers, increasing effective capacitance and out fringe capacitance.
Innovation Solution
A protection layer is formed through implantation and directional plasma treatment to prevent STI regions from being recessed during the removal of sacrificial layers, using dopants like nitrogen, carbon, and oxygen to create a higher concentration layer that enhances etching selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but STI regions become susceptible to recessing during sacrificial layer removal
Solution Approach 1:
A protection layer is formed over the STI regions before the sacrificial layer removal process. This preliminary protective measure prevents the STI regions from recessing during subsequent etching operations, allowing the use of aggressive removal processes while maintaining STI dimensional integrity.
Solution Approach 2:
The protection layer acts as an intermediary between the etchant and the STI regions. It provides etching selectivity, allowing the sacrificial layer to be removed while the protection layer shields the STI regions from damage, thus enabling high integration density without compromising STI stability.
2Reliability
If STI regions are protected from recessing, then parasitic capacitance is reduced, but additional process steps are required
Solution Approach 1:
The protection layer formation is combined with existing process steps in the fabrication sequence. By integrating the protection layer deposition into the existing工艺流程, the additional complexity is minimized while achieving the desired parasitic capacitance control.
Solution Approach 2:
The protection layer modifies the etching parameters through its material composition, providing selective protection. This parameter change enables the etching process to differentiate between the sacrificial layer and STI regions, reducing parasitic capacitance without requiring fundamentally new process equipment or methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the undesirable increase in parasitic capacitance between conductive features by protecting STI regions from recessing, maintaining device integrity and performance.
Implementation Method 1
A protection layer is formed through implantation and directional plasma treatment to prevent STI regions from being recessed
Implementation Method 2
A protection layer is formed through implantation and directional plasma treatment to prevent STI regions from being recessed
Data Source
AI summary
A method includes forming a shallow trench isolation region aside of a protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. A doping process is performed to dope a dopant into a top portion of the shallow trench isolation region to form a protection layer. The method further includes forming a dummy gate stack over the protruding fin, removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure, forming a disposable interposer in the space. The dummy gate stack is then removed, followed by an etching process to remove the disposable interposer using an etchant. In the etching process, the protection layer is exposed to the etchant. A replacement gate stack is then formed, wherein a portion of the replacement gate stack is filled in the space.